System providing for multiple virtual circuits between two...

Details System providing for multiple virtual circuits between two... System providing for multiple virtual circuits between two...

1997-09-30

2001-04-24

Martin-Wallace, Valencia (Department: 3713)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S466000

Reexamination Certificate

active

06222842

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system providing for multiple virtual circuits between two network entities for use in particular, but not exclusively, in the testing of network node apparatus providing IP messaging over an ATM network.
BACKGROUND OF THE INVENTION
As is well-known, the Internet Protocol (IP) uses a scheme of IP addresses by which every connection of a node to the Internet has a unique IP address. IP addresses are high-level addresses in the sense that they are independent of the technology used for the underlying network to which a node is connected. Each node will also have a low-level, network-dependent address (often called the MAC address) that is actually used for addressing at the network level and the IP protocol suite includes an address reolution protocol (ARP), logically positioned below the IP layer itself, that is responsible for translating between IP addresses contained in a message and the local MAC addresses.
An increasingly important technology for local area networks is ATM. ATM (Asynchronous Transfer Mode) is a multiplexing and switching technique for transferring data across a network using fixed sized cells that are synchronous in the sense that they appear strictly periodically on the physical medium. Each cell comprises a payload portion and a header, the latter including a label that associates the cell with an instance of communication between sending and receiving network end systems; this instance of communication may involve the transfer of many cells from the sending end system, possibly to multiple receiving end systems. ATM is asynchronous in the sense that cells belonging to the same instance of communication will not necessarily appear at periodic intervals.
In ATM, the labels appended to the cells are fixed-size context dependent labels, that is, they are only understandable in the light of context information already established at the interpreting network node, the label generally being replaced at one node by the label required for the next node. In other words, ATM is a virtual circuit technology requiring a set up phase for each instance of communication to establish the appropriate label knowledge at each node. Of course, to set up a desired communication, it is still necessary to identify uniquely the nodes forming the communication end points and this is achieved by using ATM addresses, generally of a significance limited to the particular ATM network concerned.
The process of sending IP messages (datagrams) over an ATM network, including the operation of the required ATM ARP system, is set out in RFC 1577 of the IETF Internet Engineering Task Force) dated January 1993. This RFC assumes an arrangement in which a sending node will only establish a single vircuit circuit to a given destination IP address (of course, this one vircuit circuit may carry multiple connections between respective pairings of high-level end points in the nodes).
FIG. 1
of the accompanying drawings is a diagram illustrating the basic mechanism by which two machines M and T exchange IP datagrams over a switched virtual circuit (SVC) established across an ATM network. The machines M and T have respective IP addresses I
M
and I
T
and respective ATM addresses A
M
and A
T
; each machine knows its own addresses. An ATMARP server S knows the IP and ATM addresses of all active nodes on the network, including machines M and T; more particularly, server S maintains an ARP table
15
associating the IP address of each node with its ATM address. The server S maintains open a respective SVC (switched virtual circuit) to each active node and the identity of this SVC is held in the ARP table
15
; thus, in the
FIG. 1
example, the server S is in communication with machine M over an SVC identified as SVC “1” at the server, and the server S is in communication with machine T over an SVC identified as SVC “2” at the server S. At machines M and T these virtual circuits are independently identified—thus at machine M its SVC to the server S is identified as SVC “3” whilst at machine T its SVC to the server S is identified as SVC “5”.
The communications interface
18
in each of the machines M and T comprises three main layers, namely: an IP layer
20
responsible for forming IP datagrams (including source and destination IP addresses) for transmission and for filtering incoming datagrams; an intermediate IP/ATM layer
21
for determining the SVC corresponding to the destination IP address of an outgoing datagram; and an ATM layer
22
, including the low-level network interface hardware, for sending and receiving datagrams packaged in ATM cells over SVCs.
The IP/ATM layer
21
maintains an ARP cache table
27
which like the table
15
of the server S contains associations between IP address, ATM address and SVC. Thus, table
27
of machine M contains an entry of the IP address Is, ATM address As, and SVC identity “3” for the server. S, and similarly, table
27
of machine T contains an entry of the IP address Is, ATM address As, and SVC identity “5” for the server S. The cache table
27
only holds information relevant to current SVCs of the machine concerned so that during the initial establishment of an SVC to a new destination, the cache table must be updated with relevant information from the ATMARP server S; this general process will be described in more detail hereinafter with reference to FIG.
2
. For the present, it will be assumed that an SVC has already been established between machines M and T and that the cache tables contain the relevant information (in particular, cache table
27
of machine M contains an entry with the IP address I
T
, ATM address A
T
, and SVC identity “4” for machine T, and cache table
27
of machine T contains an entry with the IP address I
M
, ATM address A
M
, and SVC identity “9” for machine M).
Considering now the case of a high-level application in machine M wanting to send a message to machine T, this application passes the message to the IP layer
20
together with the destination IP address I
T
IP layer
20
packages the message in one (or more) datagrams
25
A with a destination IP address of I
T
and source IP address of I
M
, Datagram
25
A is then passed to the IP/ATM layer
21
which executes an IP-to-SVC lookup task
30
to determine from table
27
the SVC to be used for sending the datagram to its destination address I
T
; in the present case, table
27
returns the SVC identity “4” and the layer
21
passes this identity together with the datagram
25
A to the ATM layer
22
which then sends the datagram in ATM cells on SVC “4”. The datagram is in due course received by machine T and passed up by layers
22
and
21
to the IP layer
20
where a filtering task
29
determines from the datagram destination address that the datagram is indeed intended for machine T; the contents of the datagram are then passed to the relevant high-level application. In the present example, this high-level application produces a reply message which it passes to the IP layer
20
together with the required return address, namely the source IP address in the received datagram
25
A. IP layer
20
generates datagram
25
B with the received return address as the destination address, the IP address I
T
of machine T being included as the source address. The datagram
25
B is passed to IP/ATM layer
21
where IP-to-SVC lookup task
30
determines from cache table
27
that the required destination can be reached over SVC “9”. This information together with datagram
25
B is then passed to ATM layer
22
which transmits the datagram in ATM cells over SVC “9” to machine M. When the datagram is received at machine M it is passed up to the IP layer
20
where it is filtered by task
29
and its contents then passed on to the relevant high-level application.
FIG. 2
of the accompanying drawings illustrates in more detail the functioning of the IP/ATM layers
21
of machines M and T in respect of datagram transmission from machine M to machine T, it being appreciated that the roles of the two layers
21
are reve

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