System oscillator gating technique for power management within a

Details System oscillator gating technique for power management within a System oscillator gating technique for power management within a

1996-07-09

1997-05-06

Sheikh, Ayaz R.

395560, G06F 132

Patent

active

056280203

ABSTRACT:
A system oscillator gating technique is provided for a power management unit of a computer system for controlling the application of power to a system oscillator. An output signal from the power management unit is provided to turn off the external system oscillator when the computer system is in a power-conserving suspend state and to turn on the external system oscillator on when the computer system resumes to a ready state. Counters are provided to control the latency of the output signal when the power management unit enters and exits the suspend state. This latency provides time for the microprocessor clock and/or other clock signals associated with the system oscillator to shut off prior to the oscillator shutdown and provides time for the oscillator to stabilize prior to the restarting of the clock signal. As a result, power consumption of the computer system may be reduced while proper clock generation for the computer system is maintained.

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