System on chip with ADC having serial test mode

Details System on chip with ADC having serial test mode System on chip with ADC having serial test mode

2000-06-19

2001-10-09

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S118000, C341S120000, C341S143000, C341S144000, C341S155000, C341S172000, C341S110000

Reexamination Certificate

active

06300889

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention pertains in general to A/D converters and, more particularly, to an analog-to-digital converter implemented in an integrated chip having a processing function associated therewith.
BACKGROUND OF THE INVENTION
Integrated circuits that incorporate processors and the such typically include some type of data conversion function. This data conversion function can either be in the form of an analog-to-digital converter or a digital-to-analog converter. In the case of the analog-to-digital converter (ADC), analog data is received on an input, sampled and the sample converted to a digital value. Each sample of the analog input signal that is converted is performed during a “conversion” cycle.
One type of ADC that is typically implemented in a processor-based system (these processor-based systems are typically referred to as a “system on a chip”) is a successive approximation converter. In the successive approximation converter, a digital-to-analog converter (DAC) is utilized to take a predefined sample output digital word and covert it to an analog value and then compare the generated analog value with the externally generated input voltage level. Each bit of the output digital word in the DAC has associated therewith a capacitor, which capacitors are binary weighted; that is, for the MSB, the capacitor is at a first value and for the next and successive bit, the capacitor is one-half that value, such that each successive bit halves the value of the previous capacitor value, the smallest being, associated with the LSB. The value of the output digital word is continually chanced to determine which combination of capacitors will result in a analog value output from the DAC substantially equal to the level of the input voltage.
One problem with ADCs when utilized in conjunction with significantly larger processing circuits is the sharing of a common clock. This can result in noise problems due to the fact that most sampling operations or conversion operations are initiated at a clock's edge. The noise that occurs at a clock's edge is due to various other processes or logic operations that are triggered from this edge. When dealing with small values of the capacitance, this noise can affect the actual analog output of the DAC that is embedded within the ADC.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein, in one aspect thereof, comprises an integrated circuit having a processing system with a system clock and a data conversion circuit that is operable to convert data between the analog and the digital domain, the data converter utilizing the system clock during normal operation. A clock isolation circuit is provided for isolating the operation of the data converter from the system clock during a test mode. A serial clock is provided for generating a serial clock during the test mode independent of a system clock. Control circuitry is then operable for controlling the data converter during the test mode to convert data utilizing the serial clock at times not coinciding with the rising and falling edges of the system clock, such control circuit operating in response to receiving a test control signal.


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patent: 5-143187-A (1993-06-01), None

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