System-on-a-chip and power gating circuit thereof

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S534000, C327S537000

Reexamination Certificate

active

07830203

ABSTRACT:
A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.

REFERENCES:
patent: 4633101 (1986-12-01), Masuda et al.
patent: 5821769 (1998-10-01), Douseki
patent: 5969564 (1999-10-01), Komatsu et al.
patent: 6118328 (2000-09-01), Morikawa
patent: 6288582 (2001-09-01), Shigehara
patent: 6784726 (2004-08-01), Burr
patent: 6876252 (2005-04-01), Kim et al.
patent: 7495506 (2009-02-01), Carper
patent: 2004/0046603 (2004-03-01), Bedarida et al.
patent: 2006/0208787 (2006-09-01), Callahan, Jr.
patent: 2007/0159239 (2007-07-01), Rhee
Article titled “New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Trasnition Mode” authored by Chang et al., 2007 IEEE International Symposium on Circuits and Systems (pp. 3740-3743).
Article titled “Minimizing inductive noise in system-on-a-chip with multiple power gating structures” authored by Kim et al., in Proc. of the European Solid-State Circuit Conference, (pp. 635-638) Sep. 2003.
Article titled “Design method of MTCMOS power switch for low-voltage high speed LSIs” authored by Mutoh et al., in Asia and South Pacific Design Automation Conference, (pp. 113-116) 1999.
Article titled “Analysis and optimization of gate leakage current of power gating circuits” authored by Kim et al., in Proc. of Asia and South Pacific Conference on Design Automation, (pp. 24-27) Jan. 2006.
Article titled “Understanding and minimizing ground bounce during mode transition of power gating structures” authored by Kim et al., in Proc. of the 29th European Solid-State Circuits Conference, (pp. 22-25) Aug. 2003.
Article titled “Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode” authored by Kim et al., in Proc. of the 2004 International Symposium on Low Power Electronics and Design, (pp. 20-25) Aug. 2004.
Article titled “Benefits and costs of power-gating technique” authored by Jiang et al., in Proc. of 2005 IEEE International Conference on VLSI in Computers and Processors, (pp. 559-566) Oct. 2005.

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