System of efficiently implementing secure hash algorithm...

Details System of efficiently implementing secure hash algorithm... System of efficiently implementing secure hash algorithm...

2003-11-12

2011-10-25

Orgad, Edan (Department: 2439)

Cryptography

Particular algorithmic function encoding

Public key

Reexamination Certificate

active

08045706

ABSTRACT:
A method of completing the Secure Hash Algorithm (SHA-1) computation in exactly 81 clock cycles with digital hardware. The general implementation techniques include: using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81-step SHA-1 computation within a single clock cycle; using a quad-output-channel 16×32-bit circular queue memory to store the 512-bit message segment (block), as a computation buffer of the Wt parameter, and to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously; using a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHA-1 computation; and using an automated controller to control internal units that perform SHA-1 and allowing external systems to access the SHA-1 computation service. The robust architecture allows for a highly efficient digital hardware implementation.

REFERENCES:
patent: 2002/0066014 (2002-05-01), Dworkin et al.
patent: 2003/0135743 (2003-07-01), Scheuermann
Secure Hash Standard FIPS publication Aug. 1, 2000, pp. 1-19.
Kang et al., 2002 IEEE Asia-Pacific Conference on ASIC proceedings, August.
Alliance Core SHA-1 Processor Product Specification, Apr. 19, 2002.
IDT QuadMUX Flow-Control Devices, 2003.
“IDT Rolls out QuadMux Flow-Control Devices Data Flow Management”, Embedded Star, Jun. 10, 2003.
Kang et al, 2002 IEEE Asia-Pacific Conference on ASIC proceedings August.

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