System of and method for efficiently performing computations...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S625000, C708S620000

Reexamination Certificate

active

06684236

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to Booth encoding, and more specifically, to efficiently performing computations through extended Booth encoding of the operands thereto.
2. Background
Many Digital Signal Processor (“DSP”) applications involve or require multiplying the sum or difference of two or more signed (two's-complement) binary numbers, (X±Y), by a third signed binary number, W, resulting in Z=W*(X±Y). In a symmetric finite impulse response (FIR) filter, for example, the separate multiplication of two samples, s
i
and s
j
, by the same coefficient, c
k
, can be replaced by the computation c
k
*(s
i
+s
j
), resulting in the savings of a multiplier. Similarly, in a multiplication of two complex numbers, each of the real and imaginary components of the product can be determined through three computations of the form C*(A+B), resulting in the saving of a multiplier. Each of these examples requires an addition before the multiplication.
In current practice, two numbers must be added in a carry-propagate adder before the multiplication can be efficiently performed. Carry-save adders are commonly used to sum multiple input vectors (K
0
+K
1
+ . . . +Kn) to produce sum and carry vectors, S and C. In current practice, S and C must be added in a carry propagate adder before the product, Z=W*(K
0
+K
1
+ . . . +Kn) can be efficiently produced.
Unfortunately, the carry-propagate adder required by these computations imposes a tradeoff between size and speed. A ripple carry adder, for example, is small but slow. In contrast, a carry-look-ahead adder, while fast, is large. No conventional adder is available which combines the size advantage of the ripple carry adder with the speed advantage of the carry lookahead adder.
Consequently, there is a need for a system for and method of performing the computation Z=W*(X±Y) which is not subject to the foregoing tradeoff between size and speed.
There is further a need for a system for and a method of performing such computations which overcomes one or more disadvantages of the prior art.
The objects and advantages of the subject invention include fulfillment of any of the foregoing needs, singly or in combination.
Additional objects and advantages will be set forth in the description which follows or will be apparent to those of skill in the art.
SUMMARY OF THE INVENTION
To achieve one or more of the foregoing objects, and in accordance with the invention as broadly described herein, there is provided, in a first embodiment of the subject invention, a system of and method for performing extended Booth encoding of two signed binary numbers, K and L. In one implementation, the extended Booth encoder converts the sum K[2n+1:2n]+L[2n+1], where L[2n]=0, into the Booth triplet M
2
[n], M
1
[n], and S[n]. In one application, this triplet can then combined with a third signed binary number W to form the partial-product vectors PP[n] which are summed to produce Z=(K+L)*W in the same manner that the triplet produced by a standard Booth encoder is used combine partial products.
A second embodiment of the subject invention comprises a system for and a method of multiplying the sum or difference of two signed binary numbers, X and Y, by a third signed binary number W.
In this embodiment, an extended Booth encoder is included for encoding the sum of the operands X and Y to form encoded data. Partial products circuitry, identical to that used with standard modified Booth encoding, is also included for forming, responsive to the encoded data, a plurality of partial products, PP. The partial products, PP, are then added or subtracted, again responsive to the encoded data, together to form Z.


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