System, method and apparatus for an instruction driven...

Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal

Reexamination Certificate

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Details

C375S240160, C375S240250, C348S699000

Reexamination Certificate

active

06414996

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to the field of digital video decoding devices, and more particularly, to a system, method and apparatus for an instruction driven digital video processor to provide motion compensation during video decoding.
BACKGROUND
The storage and/or transmission of digital audio-visual data, which typically includes not only video data and audio data, but also other data for menus, sub-pictures, graphics, control
avigation, etc., is made possible through the use of compression or encoding techniques. For example, the amount of data required to represent the video images and audio signal of a movie in an uncompressed digital format would be enormous and could not fit entirely onto a conventional recording medium, such as a compact disk (“CD”). Similarly, transmitting a movie in uncompressed digital form over a communication link (for real-time video) would be prohibitively expensive due to the large quantity of data to be transmitted and the large bandwidth required to transmit the data.
The video compression techniques typically used for storing audio-visual data on a digital video disc (“DVD”), which can hold up to 18 gigabytes of data, have been formulated by the International Standard Organization's (“ISO”) Motion Picture Experts Group (“MPEG”). The MPEG standards use a discrete cosine transform (“DCT”) algorithm to encode, or compress, the large amount of audio-visual digital data into a much smaller amount of audio-visual digital data that can be stored on a conventional recording medium. In general terms, this is accomplished by eliminating any repetitive video data, reducing the video data needed to depict movement, and eliminating any audio data that is not discernable by the human ear.
MPEG-1, which is defined in ISO/IEC 11172 and is hereby incorporated by reference, sets forth a standard format for storing and distributing motion video and audio. This standard has been used as a basis for video CDs and video games. MPEG-1 was designed for the playback of digital audio and video at a bit rate of 1.416 megabits per second (“Mbps”) (1.15 Mbps is designated for video) from data stored on a standard CD.
MPEG-2, which is defined in ISO/IEC 13818 and is hereby incorporated by reference, enhances or expands MPEG-1 to cover a wider range of applications. MPEG-2 was originally designed for the transmission of all-digital broadcast-quality video and audio at bit rates between 4 and 9 Mbps. MPEG-2, however, has become useful for may other applications, such as high definition television, and supports applications having bit rates between 1.5 and 60 Mbps.
Although the MPEG standards are typically used only for one-way communication, the H.261 and H.263 standards, which are also based on the DCT algorithm, are typically used for two-way communication, such as video telephony.
Video and/or audio compression devices, typically referred to as encoders, are used to encode a video and/or audio sequence before the sequence is transmitted or stored. The resulting encoded bitstream may then be decoded by a video and/or audio decompression device, typically referred to as a decoder, before the video and/or audio sequence is output. An encoded bitstream can only be decoded by a decoder if the encoded bitstream complies with the standard used by the decoder. Therefore, to facilitate compatibility for products produced among several manufacturers in the consumer electronics industry, the MPEG standards are being utilized for the digital video and audio decompression.
In simple terms, the DVD stores video images to be retrieved and displayed on a video display, as well as audio data to be retrieved and heard. A DVD player reads the audio-visual data stored on the DVD, decompresses and decodes the data, and generates video and audio signals for output to a video display system and audio system (i.e., to be played). In addition, DVD players typically include the capability to read, decompress and decode audio data using a variety of audio decompression techniques, such as MPEG-1, MPEG-2, PCM, Dolby AC-3 (commonly referred to as Dolby Digital), etc. Accordingly, DVD players are well-suited for playing audio-visual works, such as movies, video games, etc.
Generally, the video and audio signals are output from a DVD player to a video display (e.g. television) and a sound system (e.g. stereo system). In other words, when playing an audio-visual work, such as a movie, the DVD player reads an audio-visual stream of data from the DVD and displays the video portion of the stream (including a sub-picture portion) on the video display (television) and plays the audio portion of the stream on one or more audio speakers (stereo system).
Once the audio-visual data has been read, decompressed and decoded, the audio data must be synchronized with the video data. To facilitate the synchronized playing of the video and audio portions of the audio-visual data stream, the data stream is stored on the DVD using time stamps from a referenced frequency. The referenced frequency is defined as an integer multiple of a 27 megahertz (“MHZ”) clock. The time stamps indicate when a particular portion of the data stream is to be played, and are also used to synchronize the display of the video portion with the playing of the audio portion. As a result, the DVD player requires an integer multiple of a 27 MHZ clock to ensure that portions of the data stream are played at the appropriate time and that both the video portion and audio portion of the data stream are synchronized.
SUMMARY OF THE INVENTION
The present invention can provide a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.
The present invention can also provide a digital video processor comprising an error memory configured to store one or more error terms, a merge memory configured to store one or more filtered prediction blocks and a filter communicably coupled to the merge memory. The filter is configured to perform vertical and horizontal half-pixel interpolation on a block as dictated by a motion vector. In addition, an instruction queue configured to store one or more instructions, an execution unit communicably coupled to the instruction queue and the error memory. The execution unit is configured to receive an instruction from the instruction queue, determine whether the error memory is full and send the instruction to a motion compensation state machine for execution. The motion compensation state machine communicably coupled to the execution unit, the filter and the merge memory, the motion compensation state machine configured to execute the instruction received from the execution unit. A sum unit is communicably coupled to the error memory and the merge memory, the sum unit utilizes at least one or more error terms stored in the error memory with one or more filtered prediction blocks stored in the merge memory to produce a decoded macroblock.
In addition, the present invention provides a digital video processor comprising an error buffer, an error memory communicably coupled to the error buffer, the error memory configured to receive and store one or more error terms from the error buffer, an instruction buffer, and an instruction queue communicably coupled to the instruction buffer. The instruction queue configured to receive and store one or more instructions from the instruction buffer and a merge memory is configured to receive and store one or more filtered prediction blocks. Also included are a reference buffer, a half pixel filter communicably coupled to the reference buffer and the merge memory. The half pixel filter performs vertical and horizontal half-pixel interpolation on a prediction block received from the re

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