Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
1995-01-13
2001-03-27
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S003000, C327S007000
Reexamination Certificate
active
06208172
ABSTRACT:
BACKGROUND
The present invention concerns the monitoring of the system margin of an integrated circuit. The technique presented herein may also be used to monitor the core temperature of the integrated circuit.
The propagation delay of signals in integrated circuits is affected by many factors. These include the voltage level of VCC, process variations in production of the integrated circuit, system variations (such as input and output capacitance to the integrated circuit) and temperature.
In order to assure that timing within an integrated circuit is adequate, a system margin for the integrated circuit is utilized. That is, rather than designing output signals of the integrated circuit to be available at the last possible instant, the integrated circuit is designed so that, under optimal operating conditions, the signals arrive at the destination early. This early arrival allows for delays introduced by adverse circumstances, such as a lowered VCC, an increase in temperature and unfavorable processing variations. Thus integrated circuits are generally designed to operate sufficiently even under non-optimal conditions.
However, the trend over time in designing integrated circuits is to continue to provide integrated circuits with lower VCC and faster operating frequency. It would be advantageous therefore for purchasers of integrated circuits to be able to measure the system margin built in by the manufacturer for the purpose of evaluation and possibly to adjust the operating parameters of the integrated circuit to, where desirable, change the system margin.
In addition, in many high performance integrated circuits, operation of the integrated circuit can result in the generation of a significant amount of heat. If the amount of heat is not limited or adequately dissipated, performance of the integrated circuit can be significantly impeded and/or circuitry within the integrated circuit can be destroyed.
In order to avoid overheating integrated circuits, the integrated circuits and the system containing the integrated circuits can be designed so that even under worst case operating conditions there will not be significant enough accumulation of heat to overheat the integrated circuit. However, this over design will result in integrated circuits which will have an overabundance of system margin and which will not perform optimally under normal operating conditions.
Alternatively, some way can be devised to try to determine the temperature of the integrated circuit. For instance, this could be done by measuring the temperature on the casing of the processor chip using a thermistor or similar technique. Alternatively, a software routine can be used to monitor operation of the integrated circuit, and based on past and current operations estimating the temperature of the integrated circuits. One problem with all these methods of monitoring temperature is that they are extremely inaccurate. Additionally, the added circuitry/software may be expensive to implement.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a circuit is presented for monitoring performance of an integrated circuit. The circuit is useful for monitoring both system margin and core operating temperature of the integrated circuit.
The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit.
The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator.
The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal. A voltage level of the integrated signal indicates relative phase delay between the output signal and the clock signal.
In one embodiment, the digital signal generator includes a delay flip-flop and a gate. The delay flip-flop has a D input, a clock input and a Q output, the clock signal is connected to the clock input and the output signal is connected to the D input. The gate has a signal input, a control input and an output. The output signal is connected to the signal input. The Q output is connected to the control input of the gate. The output is connected to an input of the integrator. The integrator includes a resistor and a capacitor. The resistor has a first end connected to the output of the gate. The capacitor has a first end connected to a second end of the resistor. The capacitor also has a second end connected to a reference voltage. An analog to digital converter may be connected to the first end of the capacitor.
In this first embodiment only the falling edge of the output signal on the output pin is utilized in deriving the voltage of the integrated signal. In a second embodiment, both the falling edge and the rising edge of the output signal on the output pin are utilized to derive the voltage on the integrated signal. This increases the number of samples of the output signal on the output pin when compared with the first embodiment. However, the second embodiment uses more components, i.e., a delay flip-flop, two NAND gates and two gates, to implement the digital signal generator. Additionally, in various embodiments, more sophisticated integrators can be used to limit noise.
Additionally, in one disclosed embodiment of the present invention, the phase detection circuit includes a controller which changes an operating frequency of the integrated circuit when the voltage level of the integrated signal indicates that the phase delay between the output signal and the clock signal is longer than a predetermined value. This can be used to adjust system margin “on-the-fly” so as to assurance optimal performance of the integrated circuit.
The present invention also allows monitoring, and thus adjustment, of operating (or system) margins within an integrated circuit through monitoring phase delay of an output signal. By observing system margin, the integrated circuit can be operated at a frequency that never violates the system timing requirements regardless of conditions. This accommodates all possible worst case conditions without sacrifice to nominal operating conditions.
By monitoring phase delay of integrated circuits and adjusting operating parameters in response to excessive phase delay, it is possible to operate integrated circuits at an operating frequency which is beyond the manufacturers specified maximum frequency conditions and is optimal for the particular operating conditions.
Further, monitoring of phase delay of output signals as taught by the present invention is useful as a manufacturing aid. If system margin is detected to be below normal at ambient temperature, this indicates the system may fail when heated. Thus, using the teaching of the present invention to exactly test system margin at an ambient temperature allows a prediction of system margin at higher temperature. This reduces the need to actually test the system in a heat chamber.
In addition, various embodiments of the present invention allow for a means to monitor the internal temperature within an integrated circuit. This information allows the lowering of operating frequency of the integrated circuit when the integrated circuit is at a temperature which is above a predetermined temperature limit.
REFERENCES:
patent: 4506175 (1985-03-01), Reitmeier et al.
patent: 4520319 (1985-05-01), Baker
patent: 4858208 (1989-08-01), Swapp
patent: 5181191 (1993-01-01), Farwell
patent: 5245291 (1993-09-01), Fujimura
patent: 5291
Evoy David R.
Richardson Nicholas J.
VLSI Technology Inc.
Weller Douglas L.
Wells Kenneth B.
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