Static information storage and retrieval – Powering
Reexamination Certificate
2002-09-30
2003-11-25
Phung, Anh (Department: 2824)
Static information storage and retrieval
Powering
C365S229000
Reexamination Certificate
active
06654305
ABSTRACT:
FIELD OF THE INVENTION
In general, the present invention relates to a data-processing device. More particularly, the present invention relates to a semiconductor data processor comprising semiconductor components manufactured by using a CMOS technology.
BACKGROUND OF THE INVENTION
In recent years, the market of portable information apparatus each integrating picture and sound processing functions as well as communication functions has been growing. In order to offer apparatus having small sizes at low prices, semiconductor data processors are required to display high performance, carry out a number of functions and have small power consumption.
By virtue of a developed technology to finely fabricate semiconductor devices, a large number of transistors capable of operating at a high speed can be integrated in a single chip, and a system LSI composing a system comprising functional modules on the single chip is becoming a realistic selectable option for increasing performance and raising the number of functions.
As for reduction of power consumption, the use of a low power supply for the entire system LSI is an effective means. If the power-supply voltage for sustaining a high-speed operation is lowered, a threshold voltage of the MOS FET is also lowered as well so that the transistor (the FET) is no longer turned off completely, raising a problem of an increase in so-called sub-threshold current. The increase in sub-threshold current causes an increase in power consumption without regard to whether the system LSI is in an operating state or in a standby state. In particular, in a battery-driven data-processing apparatus, reduction of power consumption due to consumption of the sub-threshold current for lengthening the driving time is a big problem.
A typical means for sustaining both a high-speed operation and a low power consumption at a low power-supply voltage is disclosed in Japanese Patent Laid-open No. Hei8-204140. This disclosed means is referred to as a first conventional technology. An outline of what is described in this document is described as follows. The document discloses a technique whereby, in an operating state of an LSI, a P-type region of each N-type MOS transistor is biased at an electric potential higher than the ground potential but lower than a forward-direction voltage of a PN junction. On the other hand, an N-type region of each P-type MOS transistor is biased at an electric potential lower than the power-supply voltage but higher than a voltage obtained as a result of subtracting the forward-direction voltage from the power-supply voltage. By biasing the transistors in this way, the threshold voltage can be lowered and yet a high-speed operation can be carried out. Furthermore, in a standby state, the P-type region of each N-type MOS transistor is biased at a ground potential while the N-type region of each P-type MOS transistor is biased at the power-supply voltage so that the threshold voltage is increased and the sub-threshold current is reduced.
In accordance with this technology, a bias-voltage generation circuit is provided for each functional module of the system LSI. In an operating state of the functional modules, the threshold voltage of the MOS transistors is lowered to a particular level in order to implement a high-speed operation. In a standby state, on the other hand, the threshold voltage is increased to another specific level to reduce the sub-threshold current. This technology provides arbitrariness to a substrate bias voltage for setting a threshold value in an operating state. In general, if the threshold voltage is lowered, the operating speed increases but the power consumption also rises as well. In order to reduce the power consumption, it is necessary to set the substrate bias voltage at a level that gives a highest threshold voltage required for achieving a desired operating speed and a desired operating speed margin. If this substrate bias voltage is set at a fixed level by for example the bias-voltage generation circuit, however, in the case of a low power-supply voltage, in dependence on the set value of the substrate bias voltage, variations in threshold voltage result in a decrease in maximum operating frequency and/or an increase in sub-threshold current causing an increase in power consumption, which in turn raises a problem of an extremely low yield of chips. The variations in threshold voltage are caused by big variations from process to process. For this reason, it is desirable to provide the system LSI with a means for setting an optimum substrate bias voltage for each chip and for each functional module.
A technique for controlling the substrate bias of a main circuit is disclosed in Japanese Patent Laid-open No. Hei8-274620. According to this technique, a substrate-bias-dependent-type oscillation circuit sharing a substrate bias with the main circuit and an oscillation circuit for generating a signal with a frequency varying in accordance with an operating state are employed. A substrate-bias control circuit compares oscillation outputs of the 2 oscillation circuits with each other in order to synchronize one of the oscillation outputs to the other oscillation output so that the substrate bias of the main circuit can be controlled optimally in accordance with the operating frequency. The disclosed technique is referred to hereafter as a second conventional technology.
In accordance with this technology, the output of the substrate-bias-dependent-type oscillation circuit provided for each functional module is synchronized with an input clock signal serving as an operating clock signal of the functional module so that it is possible to obtain an optimum bias determined univocally in accordance with the operating clock signal. In implementation of system LSIs having uniform functions but operating frequency margins different from each other, however, there is raised a problem that it is necessary to re-design the substrate-bias-dependent-type oscillation circuits in accordance with the required margins if this technology is to be adopted.
SUMMARY OF THE INVENTION
It is thus a first object of the present invention to provide a system LSI comprising MOS transistors or, to be more specific, a system LSI capable of maintaining a high-speed operation and a low power consumption without lowering a yield and capable of finely controlling the power consumption during the operation.
It is a second object of the present invention to provide a means for increasing the yield by compensation for variations in operating frequency from system LSI to system LSI, which are caused by variations from process to process, and variations in power consumption from system LSI to system LSI, which are also caused by variations from process to process.
It is a third object of the present invention to provide a means for implementing a system LSI having any operating frequency margin from a single-design system LSI.
In general, the system LSI comprises at least two functional modules having different specific data processing speeds and different rates of utilization. Examples of the functional module are a CPU, an FPU, a DSP, a cache memory, a bus state controller, a real-time clock, a timer, a communication interface, an AD converter, a DA converter, a digital circuit and an analog circuit even though the functional module is not specially limited to these examples. Each functional module may be further divided into a plurality of internal sub-modules. From the characteristic of this configuration, in order to reduce the power consumption of the system LSI, it is important to eliminate unnecessary consumption of power by fine execution of power management for each functional module.
In order to solve the problems described above, a system LSI provided by the present invention is characterized in that the system LSI comprises substrate-bias generation circuits for generating functional modules' substrate biases independent of each other, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substr
Nishii Osamu
Tsunoda Takanobu
LandOfFree
System LSI having a substrate-bias generation circuit with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System LSI having a substrate-bias generation circuit with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System LSI having a substrate-bias generation circuit with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3162338