Patent
1996-12-20
1998-08-04
Heckler, Thomas M.
395558, 39575001, 395308, G06F 110, G06F 118
Patent
active
057908397
ABSTRACT:
A chip architecture standard merges dynamic random access memory (DRAM) macros and logic cores. The standard from merged DRAM and logic design provides the advantages of simplicity, high read and write access rates, lower power dissipation and noise suppression in system-on-chip designs. The architecture depends upon balanced clock distribution for its high performance and low clock skew to the DRAM macros and logic cores. Balanced wirings from output drivers of the control logic to corresponding inputs of the different DRAM macros minimize differences in address and control signal delays. Separated Vdd and Gnd power grids distribute power to the DRAM macros and the logic cores and incorporate decoupling capacitor arrays to provide noise suppression between the DRAM macros and logic and to minimize di/dt power supply fluctuations on chip performance.
REFERENCES:
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5537498 (1996-07-01), Bausman et al.
Hwang Wei
Luk Wing Kin
Heckler Thomas M.
International Business Machines - Corporation
Tassinari, Jr. Robert P.
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