System including phase lock loop circuit

Details System including phase lock loop circuit System including phase lock loop circuit

1997-11-10

2000-12-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327148, 331 1A, 331DIG2, 375376, H03L 706

Patent

active

061631868

ABSTRACT:
A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.

REFERENCES:
patent: 5117205 (1992-05-01), Nauta
patent: 5191239 (1993-03-01), Rogers
patent: 5220293 (1993-06-01), Rogers
patent: 5304953 (1994-04-01), Heim et al.
patent: 5552643 (1996-09-01), Morgan
patent: 5686868 (1997-11-01), Hasegawa
patent: 5783956 (1998-07-01), Ooishi
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr., 1987, "Design of PLL-Based Clock Generation Circuits", Jeong et al, pp. 255-261.

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