Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2006-07-28
2010-06-01
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S189200
Reexamination Certificate
active
07729151
ABSTRACT:
A system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via a integrated circuit buffer device) on a first signal path to the master and a second memory module simultaneously provides read data from its plurality of integrated circuit memory devices (via another integrated circuit buffer device on the second module) on a third signal path coupled to the master device. In a second mode of operation, the first memory module provides first read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on the first signal path and second read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on a second signal path that is coupled to a second memory module. An integrated circuit buffer device in the second memory module then bypasses the second read data from the second signal path and provides the second read data on a third signal path coupled to the master device.
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Hampel Craig
Shaeffer Ian
Tsern Ely
Luu Pho M.
Rambus Inc.
Vierra Magen Marcus & DeNiro LLP
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