System in package with built-in test-facilitating circuit

Details System in package with built-in test-facilitating circuit System in package with built-in test-facilitating circuit

2005-11-02

2011-10-18

Smith, Zandra (Department: 2822)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S756020, C324S763010, C257SE21503, C257SE23006, C257SE23077, C257SE23112, C438S115000, C438S118000

Reexamination Certificate

active

08040148

ABSTRACT:
This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

REFERENCES:
patent: 5000697 (1991-03-01), Murphy
patent: 5517515 (1996-05-01), Spall et al.
patent: 5919329 (1999-07-01), Banks et al.
patent: 6859054 (2005-02-01), Zhou et al.
patent: 2002/0003429 (2002-01-01), Wiggin et al.
patent: 2003/0113944 (2003-06-01), Kanamaru et al.
patent: 2004/0239349 (2004-12-01), Yamagishi et al.
patent: 2005/0225315 (2005-10-01), Goldsmith et al.
patent: 08-068832 (1996-03-01), None
patent: 08-101255 (1996-04-01), None
Notice of Reasons for Rejection, dated Jun. 14, 2011, issued by the Japanese Patent Office in Japanese Patent Application No. 2007-542193, which is the national phase patent application of PCT/JP2005/020193.

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