System having multiple phase boosted charge pump with a pluralit

Details System having multiple phase boosted charge pump with a pluralit System having multiple phase boosted charge pump with a pluralit

1994-05-20

1996-06-04

Pan, Daniel

Boots, shoes, and leggings

395550, 395750, 364DIG1, 364DIG2, 36518516, 365210, 327306, G06F 106, G06F 126

Patent

active

055242669

ABSTRACT:
An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

REFERENCES:
patent: 5140182 (1992-08-01), Ichimura
patent: 5153854 (1992-10-01), Herold
patent: 5157278 (1992-10-01), Min et al.
patent: 5216588 (1993-06-01), Bajwa et al.
patent: 5243561 (1993-09-01), Yamauchi
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5267218 (1993-11-01), Elbert
patent: 5276646 (1994-01-01), Kim
patent: 5280446 (1994-01-01), Ma et al.
patent: 5313429 (1994-05-01), Chevallier et al.
patent: 5369376 (1994-11-01), Leblebicioglu
patent: 5428568 (1995-06-01), Kobayashi et al.
1992 IEEE International Solid-State Circuits Conference, ISSCC 92 Session 9/Non-Volatile and Dynamic RAMS/Paper 9.3, "TP9.3: A 5V-Only 0.6 .mu. m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure," Masae Kurlyama, Shigeru Atsumi, Akira Umezawa, Horonori Banba, Ken-Ichi Imamiya, Klyomi Naruke, Seiji Yamada, Etsushi Obi, Mesamitsu Oshikiri, Tomoko Suzuki, Masashi Wada, Sumio Tanaka, pp. 152-153.

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