System having independently addressable bus interfaces coupled t

Details System having independently addressable bus interfaces coupled t System having independently addressable bus interfaces coupled t

1994-10-31

1997-03-25

Lee, Thomas C.

395864, 395823, 395290, 39542101, G06F 1312

Patent

active

056154046

ABSTRACT:
A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

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