System having different signal transfer modes for detecting and

Telecommunications – Receiver or analog modulated signal frequency converter – Signal selection based on frequency

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395306, 395280, 395500, 395834, 455 261, 36492793, 3642402, 364135, 3642216, G06F 1300, G06F 1320

Patent

active

055242170

ABSTRACT:
To enable wired-OR signal lines to be connected without interlock in a bus linkage unit for connecting the bus of a computer system with the bus of an expansion device or the bus of another computer system through a signal transfer path in which the signal mode is different from those of the buses. A shadow register 46 that acts on the level of wired-OR signal line 51 of the other bus is provided in each system. The level of wired-OR signal lines in each system is sent to the shadow register of the other system through a communication path. When the shadow register of the system is at a predetermined level, said system will not send the level of said wired-OR signal line to the other system. Interlock is eliminated by avoiding repetition of level transfer echoes between both systems in this way. Both systems are further provided with a shadow-shadow register 47 for forming a mirror image of the shadow register of the other system. A predetermined level will be sent to the shadow register of the other system based on the nonconformity between the level of the shadow-shadow register in each system and the level of wired-OR signal line of said system.

REFERENCES:
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patent: 5014284 (1991-05-01), Langer et al.
patent: 5101477 (1992-03-01), Casper et al.
patent: 5257289 (1993-10-01), Jopson
patent: 5289459 (1994-02-01), Brownlie
International Business Machines Technical Disclosure Bulletin: vol. 28, No. 6, pp. 2346-2347, "Stackable Unit Packaging Concept" (Nov. 1985).
International Business Machines Technical Disclosure Bulletin: vol. 26, No. 10A, pp. 5147-5152 "Extended Data Bus with Direction and Enable Control Features" (Mar. 1984).
International Business Machines Technical Disclosure Bulletin: vol. 19, No. 8, pp. 3139-3143, "Serial Channel to I/O Interface" Jan. 1977.
"Analysis of a GaAs E-D Inverter Chain", Omar Wing, 1989, IEEE, pp. 1141-1144.

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