System having an address generating unit and a log comparator pa

Details System having an address generating unit and a log comparator pa System having an address generating unit and a log comparator pa

1990-03-09

1992-05-12

Lee, Thomas C.

Boots, shoes, and leggings

3642328, 3642402, 3642434, 36424341, 3642526, 3642563, 3642564, 3642565, 3642592, 364DIG2, G06F 934, G06F 1210, G06F 1316

Patent

active

051135060

ABSTRACT:
A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.

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