Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
1999-10-13
2004-03-30
Ellis, Richard L. (Department: 2183)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S027000, C712S209000, C712S227000
Reexamination Certificate
active
06714904
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods for increasing the efficiency of operation of a microprocessor which dynamically translates instructions from a target instruction set to a host instruction set and speculates on translated operations.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a “target” processor having an instruction set different than the instruction set of the morph host processor. The morph host processor executes the code morphing software to translate the application programs dynamically into morph host processor instructions able to accomplish the purpose of the original target software. As the target instructions are translated, the new host instructions are both executed and stored in a translation buffer where they may be accessed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required for hardware to execute a program are eliminated. The new microprocessor has demonstrated that a simple fast processor designed to expend little power is able to execute translated “target” instructions at a rate equivalent to that of the “target” processor for which the programs were designed.
In order to be able to run programs designed for other processors at a rapid rate, the morph host processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer which resides between the host processor and the translation buffer. A second enhancement is a set of host registers (in addition to normal working registers) which store known state of the target processor at the beginning of any sequence of target instructions being translated. Memory stores generated as sequences of morph host instructions are executed are placed in the gated store buffer. If the morph host instructions execute without raising an exception, the target state at the beginning of the sequence of instructions is updated to the target state at the point at which the sequence of translated instructions completed and the memory stores are committed to memory.
If an exception occurs during the execution of a sequence of host instructions, processing stops; and the entire operation may be returned to the beginning of the sequence of instructions at which known state of the target processor exists. This allows very rapid and accurate handling of exceptions, a result which has never been accomplished by the prior art.
It will be noted that the method by which the new microprocessor handles the execution of translations by placing the effects generated by execution in temporary storage until execution of the translation has been completed is effectively a very rapid method of speculation. The new microprocessor, in fact, uses the same circuitry for speculating on the outcome of other operations. For example, by temporarily holding the results of execution of instructions reordered by a software scheduler from naively translated instructions, more aggressive reordering may be accomplished than has been attempted by the prior art. When such a reordered sequence of instructions executes to produce a correct result, the memory stores resulting from execution of the reordered sequence may be committed to memory and target state may be updated. If the reordered sequence generates an exception while executing, then the state of the processor may be rolled back to target state at the beginning of the sequence and a more conservative approach taken in translating the sequence.
One of the most advantageous features of the new microprocessor is its ability to link together long sequences of translated instructions. Once short sequences of target instructions have been translated and found to execute without exception, it is possible to link large numbers of these short sequences together to form long sequences of instructions. This allows a translated program to be executed at great speed because the microprocessor need not go through all of the steps (such as looking up each of the shorter translated sequences) normally taken by hardware processors to execute instructions. Even more speed may be attained than might be expected because, once long sequences are linked, it is often possible for an optimizer to eliminate many of the steps from the long sequences without changing the results produced. ,Hardware, optimizers have never been able to handle sequences of instructions long enough to allow the patterns which allow significant optimization to become apparent.
A problem which has occurred with the new processor relates to sequences of instructions which are executed only an insignificant number of times. For example, instructions required to initiate operation of a particular application program are often executed only when the application is first called; and instructions required to terminate operation of an application are often executed only when the program is actually terminated. The original embodiment of the new processor typically treated all instructions in the same manner. It would decode a target instruction, generate the primitive host instructions which carry out the function for which the target instruction is designed, optimize the sequence of host instructions, and then store the translated and optimized instructions in the translation buffer. As the operation of the new processor proceeded, the sequences of translated instructions would be linked to one another and further optimized; and the longer sequences of linked instructions would be stored in the translation buffer. Ultimately, large blocks of translated instructions were stored as super-blocks of host instructions. When an exception occurred during execution of a particular host instruction or linked set of instructions, the new processor would go through the process of rolling back to the last correct state of the target processor and then provide single-step translations of the target instructions from the point of the last correct state to the point at which the exception again occurs. These translations would also be stored in the translation buffer. This embodiment of the new processor is described in detail in U.S. Pat. No. 5,832,205, Kelly et al., issued Nov. 3, 1998, and assigned to the assignee of the present invention.
Although this process creates code which executes rapidly, the process has a number of effects which limit the overall speed attainable and may cause other undesirable effects. First, the process requires a substantial amount of storage capacity for translated instructions. Many times a number of different translations exist for the same set of target instructions because the sequences were entered from different branches. Once stored, the translated instructions occupy the translation buffer until removed for some affirmative reason. Second, if a sequence of instructions is to be executed only a few times, the time required for translating and optimizing may be significantly greater than that needed to execute a step-by-step translation of the initial target instructions. The optimization of little used sequences of translated instructions tends to lower the average speed of the new processor.
For these reasons, the described embodiment of the new processor was modified to include as a part of the code morphing software, an interpreter which accomplishes step-by-step translation of each of the target instructions. An interpreter essentially fetches a target instruction, decodes the instruction, provides a host process to accomplish the purpose of the target instruction, and executes the host process. When it finishes interpreting and executing one target instruction, the state of the target processor is brought up to date; and the interpreter proceeds to the next target instruction. This process essentially single
Keppel David
Torvalds Linus
Ellis Richard L.
Transmeta Corporation
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