Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-16
2004-11-02
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185270, C365S185030
Reexamination Certificate
active
06813189
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to a system for using a dynamic reference in a double-bit cell memory.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as memory devices, are commonly used as information storage devices in digital systems. As the amount of information that needs to be stored increases, it has become increasingly important to have an efficient way of accessing such memory devices.
Generally, memory read or write operations are initiated in response to external signals provided to the memory by a controller, such as a processor. In most cases, the amount of information that needs to be transferred during a memory access is large. In addition, the rate at which the information is propagated from a processor to a memory device and vice versa continues to increase. Therefore, increasing performance demands are being placed on the ability to read and write information to memory devices.
In one type of FLASH memory architecture, referred to as “mirror bit” or “double bit” FLASH memory, there are two data bits stored at each core memory cell. During operation of the memory, reference cells are used to perform various memory functions. For example, there is a dynamic reference read method where an average of voltage threshold (Vt) values for data
01
and data
10
is used to program the reference cells, which are programmed and erased along with the core cells in a memory sector. Because data
01
and
10
have a Vt distribution, the associated reference cells will have Vt distribution as well. If the data
01
and
10
Vt distributions are wide, the reference cell Vt distribution becomes wide, and as a result, operational margins between the reference cell and the data
01
and data
10
will be greatly reduced.
FIG. 1
illustrates how reference Vt distributions are determined in a conventional mirror bit memory where reference cells are placed in the core memory array area. Because core cell data
10
and
01
have wide Vt distributions, the Vt distribution for the reference cell is also wide, as shown at
102
. For example, the center line
104
indicates the center of one range of distribution for data
10
and
01
Vt values, and the center line
106
indicates the center of another range of distribution for data
10
and
01
Vt values. As a result, the wide Vt distribution shown at
102
will result. As the reference cell Vt distribution becomes wider, the sense margin regions
108
,
110
become smaller. Thus, as the sense margin decreases, memory read errors increase, and so the performance of the memory decreases.
Therefore, it would be desirable to have a way to set the voltage thresholds of reference cells in a core array to achieve the optimal sense margins for the best memory performance.
SUMMARY OF THE INVENTION
The present invention includes a system for using a dynamic reference cell with core cells in a dual-bit memory device. The system includes a method for programming the dynamic reference cell in order to provide the optimal sense margin between the Vt of the dynamic reference and the Vt of the data “10” or “01” core cell values during read operations. The system includes method and apparatus for reading the core cells based on the dynamic reference.
In one embodiment of the present invention, a method is provided for programming a double bit core cell in a memory device. The memory device includes a dynamic reference cell and a fixed reference cell. The method comprises the steps of programming the dynamic reference cell using the fixed reference cell, and programming the double bit core cell using the dynamic reference cell.
In one embodiment of the present invention, apparatus is provided for programming a double bit core cell in a memory device, wherein the memory device includes a fixed reference cell. The apparatus comprises a dynamic reference cell that is programmed based on the fixed reference cell, and wherein the double bit cell is programmed based on the dynamic reference cell. The apparatus also comprises a current circuit that adjusts a core cell current to provide a current difference between the core cell and the dynamic reference cell during a program verify operation.
REFERENCES:
patent: 6373767 (2002-04-01), Patti
patent: 6490203 (2002-12-01), Tang
Fujitsu Limited
Ho Hoai
Sheppard Mullin Richter & Hampton LLP
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