System for use in translating virtual addresses into absolute ad

Details System for use in translating virtual addresses into absolute ad System for use in translating virtual addresses into absolute ad

1995-03-31

1997-07-15

Moore, David K.

G06F 926, G06F 934, G06F 1200, G06F 1202

Patent

active

056491409

ABSTRACT:
In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

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