System for triggering direct memory access transfer of data betw

Details System for triggering direct memory access transfer of data betw System for triggering direct memory access transfer of data betw

1996-05-07

1998-06-09

Lee, Thomas C.

395842, 395446, G06F 1300

Patent

active

057650411

ABSTRACT:
Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

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Computer Design, "Dynamic FIFO Speeds Controller Throughput", Apr. 1, 1987, 26, No. 7, Littleton, MA, p. 47.

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