System for translating virtual address to real address by duplic

Details System for translating virtual address to real address by duplic System for translating virtual address to real address by duplic

1992-05-27

1995-09-12

Lee, Thomas C.

Boots, shoes, and leggings

3642543, 3642563, 3649571, 364DIG1, 395413, G06F 1210

Patent

active

054505585

ABSTRACT:
Disclosed is an apparatus and method which combines the mask information with the virtual page number in each block entry of a translation lookaside buffer of a virtual memory system. The invention defines a range of pages that are translated by a block entry, thus providing space in the virtual page number for the mask bits. The mask information is duplicated in the real page number of the block entry that corresponds to the virtual page number. This duplication allows the mask information to be easily sent to the bus driver circuits where it is needed to select the bits that form the real page number.

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E. DeLano, W. Walker, J. Yetter and M. Forsyth, "A High Speed Superscalar PA-RISC Processor", presented at the proceedings of the Compcon Spring 1992, Digest of Papers, Feb. 24, 1992.

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