Boots – shoes – and leggings
Patent
1989-08-09
1991-09-03
Lall, Parshotam S.
Boots, shoes, and leggings
371 27, G01R 3128
Patent
active
050460331
ABSTRACT:
The present system is employed to generate and transmit information which is needed to construct or assemble truth tables and pertinent data which are directed to associated circuits which require testing. The present method employs a technique whereby information is nested, or compacted, in accordance with certain rules of grammar and is transmitted from a circuit design group to a vendor, i.e., a manufacturer of the circuit designed by a design group. When the nested information is expanded by a translator device, or by a translation program, at the manufactuer's location, it is directly expandable into truth table information for use by various logic testers. Each of the truth tables defines a specific function that the designer wants tested in the associated circuit. The manufacturer supplies the test platform hardware which generates the desired signal patterns defined by the truth table information and pertinent data. The present method is employed to more efficiently compact and transmit information which is ultimately translated into truth table and test data information to effect a test program for various test platforms. By way of example, in the present description, the circuit to which the compacted information is applicable is a hybrid semiconductor multicircuit package and the test information relates to test of the semiconductor chips in wafer form as well as the chips before and after being mounted in package form.
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Andreasen David A.
Hackney Gregory P.
Shea Dean J.
Lall Parshotam S.
Ramirez Ellis B.
Scott Thomas J.
Sowell John B.
Starr Mark T.
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