Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1995-12-29
1999-01-12
Lee, Thomas C.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
345488, 345853, 345894, H01J 1300, G06F 764
Patent
active
058599908
ABSTRACT:
The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration.
It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than a recall with a cacheline size, and the current transfer adders is a multiple of the cacheline size.
The present invention also provides a computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access controller (DMA). The DMA performs DMA transactions between the first and second buses. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus. The error handling logic aborts a DMA transfer when the error signal is asserted and the retry signal is deasserted.
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Intel Corporation
Lee Thomas C.
Perveen Rehana
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