System for transferring data between an interleaved main memory

Details System for transferring data between an interleaved main memory System for transferring data between an interleaved main memory

1987-08-27

1990-04-03

Zache, Raulfe B.

Boots, shoes, and leggings

3642423, 3642464, 3642513, 3642541, 3642544, 3642549, G06F 1206, G06F 1328

Patent

active

049145754

ABSTRACT:
An input/output channel apparatus includes a system bus controller for generating a memory read request and outputting a memory address. Generation of the memory read request is inhibited in response to a request inhibit instruction generated by a request-inhibit generating section. When a memory bank other than one accessed in response to the immediately preceding memory read request is accessed, the request-inhibit instruction is generated. The request-inhibit instruction is canceled when memory interleaved data on the basis of the memory read requests for the same memory bank are input to a buffer in the apparatus.

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