Patent
1995-07-20
1998-09-01
Lee, Thomas C.
395307, 395854, 395872, G06F 1116, G06F 1320
Patent
active
058023925
ABSTRACT:
A system is provided for transferring 32-bit data words between a 32-bit host personal computer and an IDE peripheral storage device adapted to transfer data as 16-bit words and store the data in a data register identified by an offset address. The system microprocessor transfers 32-bit data words from an internal 32-bit data transfer register in two sequential 16-bit words without an intervening input or output instruction and automatically increments the offset address associated with the second 16-bit word. A device driver program or a peripheral BIOS directs the microprocessor to address data transfers from the 32-bit register to an alias address, the offset address portion of which is incremented for the second 16-bit word. An interface adapter circuit is provided which includes logic circuitry for recognizing an address as an alias, and translating the offset portion of the alias address to offset address associated with the peripheral's data register.
REFERENCES:
patent: 4438512 (1984-03-01), Hartnug et al.
patent: 4905184 (1990-02-01), Giridhar et al.
patent: 5295247 (1994-03-01), Chang et al.
patent: 5581715 (1996-12-01), Verinsky et al.
patent: 5592682 (1997-01-01), Chejlava, Jr. et al.
Epstein Jeffrey E.
Heppenstall Mark F.
Future Domain Corporation
Lee Thomas C.
Perveen Rehana
LandOfFree
System for transferring 32-bit double word IDE data sequentially does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for transferring 32-bit double word IDE data sequentially, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for transferring 32-bit double word IDE data sequentially will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-282946