System for testing internal nodes in receive and transmit FIFO's

Details System for testing internal nodes in receive and transmit FIFO's System for testing internal nodes in receive and transmit FIFO's

1991-02-12

1992-10-06

Nguyen, Vinh

Electricity: measuring and testing

Plural, automatically sequential tests

324158R, 371 151, 371 221, G01R 3128

Patent

active

051535092

ABSTRACT:
A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.

REFERENCES:
patent: 4336495 (1982-06-01), Hapke
patent: 4667330 (1987-05-01), Kumagai
patent: 4743841 (1988-05-01), Takeuchi
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4827476 (1989-05-01), Garcia
patent: 4835774 (1989-05-01), Ooshima et al.

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