System for testing instruction queue circuit and central process

Details System for testing instruction queue circuit and central process System for testing instruction queue circuit and central process

1994-08-26

1996-03-05

Beausoliel, Jr., Robert W.

Boots, shoes, and leggings

3642653, 371 212, G06F 1154, G06F 100, G11C 2900

Patent

active

054974593

ABSTRACT:
In a system for testing an instruction queue circuit connected to an external memory via a bus controller provided in a processor having a microprogram control unit, an operation unit connected to the microprogram control unit and connected, via an internal bus, to the instruction queue circuit, the instruction queue circuit-including a plurality of queue buffers, a writing unit writes internal bus information transferred via the internal bus into the instruction queue circuit in response to a first instruction generated by the microprogram control unit. The internal bus information is contained in the first instruction. A reading unit reads the internal bus information from the instruction queue circuit in response to a second instruction generated by the microprogram control unit. A gate circuit outputs the internal bus information to the internal bus in response to a third instruction generated by the microprogram control circuit. The internal bus information is used to test the instruction queue circuit.

REFERENCES:
patent: 4156926 (1979-05-01), Hartman
patent: 4327408 (1982-04-01), Foissell et al.
patent: 4546430 (1985-10-01), Moore et al.
patent: 4730318 (1988-03-01), Bagholtz, Jr. et al.
patent: 5016220 (1991-05-01), Yamagata
patent: 5226149 (1993-07-01), Yoshida et al.
Computer System Architecture, 2nd Ed., M. Morris Mano, 1982, Prentice Hall, Inc. Englewood Cliffs, NJ 07632, pp. 52-54, and pp. 356-358.

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