System for testing digital circuits

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371 224, G01R 3128

Patent

active

049264257

ABSTRACT:
Test node equipment is provided between successive component groups operating in cascade and each test node is connected to a data bus system through which test patterns can be provided by a test pattern generator and from which signals can be evaluated by a test pattern analyzer, the test pattern generator and the test pattern analyzer being under control of a test computer. Each test node has a state in which the output of the preceding component group passes through it to the next component group with only a possibility of monitoring possible deficiencies by the test computer and other states in which the cascade operation of component groups can be interrupted at a test node for inserting a test pattern to a following component group or receiving a processed test pattern from a preceding component group. A test node may also contain driver circuits for transfer of rapid data to a memory of the test computer for subsequent processing at a lower speed and may also contain equipment to assist in the use of a so-called signature analysis system.

REFERENCES:
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patent: 4594711 (1986-06-01), Thatte
patent: 4701922 (1987-10-01), Kuboki et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4718065 (1988-01-01), Boyle et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4780666 (1988-10-01), Sakashita et al.

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