System for testing bumped semiconductor components with...

Details System for testing bumped semiconductor components with... System for testing bumped semiconductor components with...

2001-12-04

2002-10-15

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06466047

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture, and specifically to an interconnect and system for testing bumped semiconductor components, such as bumped semiconductor dice contained on wafers, or bumped semiconductor packages contained on panels. This invention also relates to test systems and test methods employing the interconnect.
BACKGROUND OF THE INVENTION
Semiconductor components, such as dice, wafers, chip scale packages, and BGA devices can include terminal contacts in the form of bumps, or balls. This type of component is sometimes referred to as a “bumped” component, and the terminal contacts are sometimes referred to as “bumped contacts”.
The bumped contacts provide a high input/output capability for a component, and permit the component to be surface mounted, or alternately flip chip mounted, to a mating substrate, such as a printed circuit board (PCB). Typically, the bumped contacts comprise solder balls, which permits bonding to the mating substrate using a solder reflow process. For some components, such as chip scale packages and BGA devices, the balls can be arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA).
Bumped components are often manufactured using wafer level processes wherein multiple components are fabricated on a substrate, which is then singulated into individual components. Bumped semiconductor dice, for example, can be fabricated on silicon wafers which are then singulated into individual bumped dice. Chip scale packages can also be fabricated using a wafer, or a panel of material, such as silicon, ceramic, or a glass filled resin.
The wafer level fabrication processes also require wafer level testing procedures, in which temporary electrical connections are made with the bumped contacts, and test signals are transmitted to the integrated circuits contained on the components. The testing procedures can be performed using a test system in which an interconnect component of a test system, such as a probe card, makes the temporary electrical connections with the components. For example, a typical wafer level test system for testing semiconductor wafers includes a wafer prober for handling and positioning the wafers, a tester for generating and analyzing test signals, a probe card for making temporary electrical connections with the wafer, and a prober interface board for routing test signals from the tester pin electronics to the probe card.
There are several problems associated with wafer level testing of bumped components. Firstly, the interconnect must make low resistance electrical connections with the bumped contacts, which requires penetration of oxide layers on the contacts. However, bumped contacts are easily deformed, making low resistance connections difficult to make without deforming the bumped contacts. In general, deformed contacts present cosmetic and performance problems in the completed components.
In addition, the bumped contacts are typically contained in dense arrays, such that a substrate, can include thousands of bumped contacts. During testing procedures, it is difficult to physically and electrically contact large numbers of bumped contacts with conventional interconnects, such as probe cards. In addition, the testers associated with the test systems may not have sufficient resources to simultaneously generate and analyze test signals for large numbers of bumped contacts.
The present invention is directed to an interconnect and test system for wafer level testing of bumped components, capable of making reliable electrical connections with dense arrays of bumped contacts. In addition, the interconnect on-board multiplex circuitry configured to expand the resources of a tester of the test system during test procedures.
SUMMARY OF THE INVENTION
In accordance with the present invention, an interconnect for testing bumped semiconductor components contained on a component substrate, such as a wafer, or a panel of material, is provided. Also provided is a test system which includes the interconnect, and a tester for generating test signals and analyzing the resultant signals.
The interconnect includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Several different embodiments for the interconnect contacts are provided. In a first embodiment, the interconnect contacts comprise conductive pockets sized and shaped to retain and electrically engage the bumped contacts. In a second embodiment, the interconnect contacts comprise conductive pockets having blades for penetrating the bumped contacts. In a third embodiment, the interconnect contacts comprise penetrating projections projecting from a surface of the interconnect substrate. In a fourth embodiment, the interconnect contacts comprise conductive pockets formed on an elastomeric layer.
In addition to the interconnect contacts, the interconnect includes an on board multiplex circuit adapted to fan out, and selectively transmit, test signals from the tester to the contacts in response to control signals. The multiplex circuit includes integrated circuitry and active electrical switching devices, such as FETs, operable by control signals generated by a controller. With the interconnect substrate comprising a semiconducting material, the active electrical switching devices, can be formed directly on the interconnect substrate, using semiconductor circuit fabrication techniques. Alternately, the multiplex circuit can be contained on a die physically and electrically attached to the interconnect, or on an interposer attached to the interconnect.
The interconnect can be configured to electrically engage one component, or multiple components at the same time, up to all of the components contained on the component substrate. Each interconnect contact can be enabled or disabled as required by the multiplex circuit, to selectively write (send) the test signals to the components, and to selectively read (receive) output signals from the components. In addition, the multiplex circuit allows tester resources to be fanned out to multiple components under test, while maintaining the uniqueness of each component, and the ability to disconnect failing components. The additional control of the test signals also speeds up the testing process, and allows higher wafer throughputs using the same tester resources.
A test procedure conducted with the test system includes the step of testing the bumped components for opens and shorts in groups corresponding to the available tester resources. Next, multiple components can be written to in parallel by multiplexing drive only and I/O resources of the tester. Following the write step, multiple components can be read in parallel in groups corresponding to the available tester drive only and I/O resources.


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