System for superposition of the successive stages of the transfe

Details System for superposition of the successive stages of the transfe System for superposition of the successive stages of the transfe

1980-11-25

1984-02-21

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 700

Patent

active

044333757

ABSTRACT:
A control logic circuit (C) is provided in each unit such as processors and memories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission bus only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.

REFERENCES:
patent: 4271465 (1981-06-01), Ohtsuka et al.
patent: 4296463 (1981-10-01), Dalboussiere et al.
patent: 4314335 (1982-02-01), Pezzi

Affiliated with

Also associated with

Rating

System for superposition of the successive stages of the transfe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for superposition of the successive stages of the transfe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for superposition of the successive stages of the transfe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1038935