System for simulating memory arrays in a logic simulation machin

Details System for simulating memory arrays in a logic simulation machin System for simulating memory arrays in a logic simulation machin

1986-04-22

1989-08-29

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642323, 364243, 3642448, G06F 1516, G06F 944, G06F 938, G06F 1312

Patent

active

048623474

ABSTRACT:
A method and apparatus for simulating memory devices in a logic simulation machine include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM. Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

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