System for selectively communicating instructions from memory lo

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3642292, 3642293, 3642318, 3642319, 3642407, 364246, 3642624, 36493141, 3649462, 364DIG1, G06F 900, G06F 1300, G06F 1516

Patent

active

051215020

ABSTRACT:
A horizontal architecture computer in which a plurality of instructions are selectively communicated to a processing unit simultaneously or sequentially. The computer includes a processing unit with a plurality of processors, an instruction unit with a plurality of storage locations for storing instructions, and means for communicating the instructions to the processors. A first connection circuit provides a plurality of parallel communication channels between the storage locations and the processors and a second connection circuit provides a single serial communication channel between the storage locations and the processors. The first circuit is selected if a multioperation instruction is to be executed, otherwise the second circuit is selected instead.

REFERENCES:
patent: 4031521 (1977-06-01), Hall et al.
patent: 4037213 (1977-07-01), Atkins et al.
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 4166289 (1979-08-01), Murtha et al.
patent: 4251861 (1981-02-01), Mago
patent: 4292667 (1981-09-01), Catiller et al.
patent: 4310879 (1982-01-01), Pandeya et al.
patent: 4400768 (1983-08-01), Tomlinson et al.
patent: 4462074 (1984-07-01), Linde
patent: 4466061 (1984-08-01), DeSantis et al.
patent: 4467422 (1984-08-01), Hunt
patent: 4521874 (1985-06-01), Rau et al.
patent: 4553203 (1985-10-01), Rau et al.
patent: 4556938 (1985-12-01), Parker et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4720780 (1988-01-01), Doliecek
patent: 4720784 (1989-01-01), Rathkrishnan et al.
patent: 4740894 (1988-04-01), Lyon et al.
patent: 4792945 (1988-12-01), Mark
patent: 4833605 (1989-05-01), Terada et al.
patent: 4833655 (1989-05-01), Wolf et al.
patent: 4837676 (1989-06-01), Rosman
Rau, et al., Efficient Code Generation for Horizontal Architectures: Compiler Techniques And Architectural Support, IEEE 1982, pp. 131-139.
Rau, et al., Some Scheduling Techniques And An Easily Schedulable Horizontal Architecture For High Performance Scientific Computing, IEEE 1981, pp. 183-198.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System for selectively communicating instructions from memory lo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for selectively communicating instructions from memory lo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for selectively communicating instructions from memory lo will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1812186

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.