System for scan testing of logic circuit networks

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

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371 223, G01R 3128

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051554321

ABSTRACT:
The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 4177452 (1979-12-01), Balasubramanian et al.
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4494066 (1985-01-01), Goel et al.
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4638246 (1987-01-01), Blank et al.
patent: 4782283 (1988-11-01), Zasio
Fordham 1987 Spring Catalog; Fordham Radio, Hauppauge, N.Y.; 1987; p. 77.
"Fault Simulation for Pass Transistor Circuits Using Logic Simulation Machines," by Barzilai et al., IBM Tech. Disc. Bull., vol. 27, #5, Oct. 1984, pp. 2861-2864, cl. 371-23.
S. Funatsu, N. Wakatsuki, A. Yamada, "Designing Digital Circuit With Easily Testable Consideration", 1978 IEEE Semiconductor Test Conference, pp. 98-102, 1978.
L. A. Stolte and N. C. Berglund, "Design For Testability For The IBM System/38", 1979 IEEE Conference, Session 2, pp. 29-36, 1979.
Kyushik Son and D. K. Pardhan, "Design of Programmable Logic Arrays For Testability," 1980 IEEE Conference, paper 7.2, pp. 163-166, 1980.
Erwin Trischler, "Incomplete Scan Path With An Automatic Test Generation Methodology", 1980 IEEE Test Conference, Paper 7.1, pp. 153-161, 1980.
Y. Arzoumanian and J. Waicukauski, "Fault Diagnosis In An LSSD Environment," 1981 IEEE Conference, paper 4.2, pp. 86-88, 1981.
Mark W. Levi, "CMOS Is Most Testable," 1981 IEEE Test Conference, paper 9.3, pp. 217-220, 1981.
S. Dasqupta, et al., "A Variation of LSSD and Its Implications On Design And Test Pattern Generation In VLSI," 1982 IEEE Test Conference, paper 3.3, pp. 63-65, 1982.
K. S. Ramanatha and N. N. Biswas, "A Design For A Complete Testability of Programmable Logic Arrays," 1982 IEEE Conference, paper 3.4, pp. 67-74, 1982.
David M. Singer, "Testability Analysis of MOS VLSI Circuits," 1984, IEEE International Test Conference, paper 21.1, pp. 690-696, 1984.
I. M. Bengali, V. J. Coli, and F. Lee, "Diagnostic Devices In Algorithms For Testing Digital Systems," Monolithic Memories Systems Design Handbook, Second edition, pp. 3-3 to 3-13.
V. J. Coli, S. M. Donovan, and F. Lee, "High Speed PROMS With On Chip Registers and DIagnostics," Monolithic Memories System Design Handbook, Second Edition, pp. 3-15 to 3-25.
E. H. Frank and R. F. Sproull, "Testing and Debugging Custom Integrated Circuits", 1981, Computing Surveys, vol. 13, No. 4, pp. 425-451.

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