System for retaining state data of an integrated circuit

Details System for retaining state data of an integrated circuit System for retaining state data of an integrated circuit

2011-06-07

2011-06-07

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Flip-flop

C365S049160, C365S226000

Reexamination Certificate

active

07957172

ABSTRACT:
According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.

REFERENCES:
patent: 5787273 (1998-07-01), Runaldue
patent: 6973101 (2005-12-01), Grivna
patent: 7372928 (2008-05-01), Foley et al.
patent: 2002/0087928 (2002-07-01), Six
patent: 2005148837 (2005-06-01), None

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