System for reordering of instructions before placement into cach

Details System for reordering of instructions before placement into cach System for reordering of instructions before placement into cach

1995-01-25

1998-04-21

Ellis, Richard L.

395380, G06F 930

Patent

active

057427844

ABSTRACT:
A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.

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