Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Reexamination Certificate
2000-03-17
2004-09-21
Williams, Kimberly (Department: 2626)
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
C358S435000, C358S296000, C382S168000, C382S232000
Reexamination Certificate
active
06795218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for compressing data which is located between a sensor and a transmission unit. The invention applies particularly well to remote sensing satellites which acquire image data and then transmit it to a ground station via a radio transmission channel one characteristic of which is that it is able to convey information only at a constant bit rate.
2. Description of the Prior Art
The volume of information acquired by the sensor is generally greater than the volume of information that the transmission channel can transmit. This is true in particular for remote sensing satellites because of the increased number and resolution of onboard sensors. Consequently, it is necessary to employ data compression processes to reduce the quantity of information to be transmitted for the same volume of information acquired by the sensor.
However, because of the inherent nature of the compression processes, the output bit rate of the compressor is directly proportional to the entropy of the input signal. The quantity of information to be transmitted therefore generally varies with time because the characteristics of the input signal themselves vary with time.
To optimize the use of the transmission channel it is therefore necessary to minimize these bit rate fluctuations at the output of the compression system by regulating the bit rate.
In the situation where the transmission channel requires a constant bit rate, this regulation becomes essential.
FIG. 1
is an extremely schematic representation of the architecture of a signal processing system in the context of the invention. This architecture takes the form of a processing system comprising a chain of processing units.
The unit
1
is a sensor. It can be an optical or infrared video camera on board a remote sensing satellite, for example.
The unit
2
is a compressor.
The unit
3
is a bit rate regulator.
The unit
4
is a backing store which serves as a cache memory for the transmission unit
5
. In the case of a remote sensing satellite, the transmission channel is not always available, in particular because of the time limit on the line of sight between the satellite and the ground stations. It must therefore be possible to store data during these periods in which the transmission channel is not available.
The flow of data can pass through the backing store
4
or not, depending on the availability of the transmission channel.
FIG. 2
is a schematic representation of a first embodiment of the regulator.
A buffer B
1
is inserted between the compressor C
1
and the backing store M
1
. A regulator R
1
detects when the buffer B
1
is full and then interrupts the acquisition of data.
To comply with the constraint of a constant bit rate on the transmission channel, non-significant data is transmitted when the buffer B
1
is empty.
Because non-significant data is transmitted, the bit rate on the transmission channel is not the optimum bit rate. This solution is therefore unsatisfactory.
A second solution is disclosed in French patent 2 707 070, whose title in translation is Variable bit rate compression image processing system. The patentee is the Centre National d'Études Spatiales (CNES).
FIG. 3
is a schematic representation of the system.
As in the previous solution, a buffer memory B
2
is inserted between the compressor C
2
and the backing store M
2
. A regulator R
2
knows the filling level L
B
of the buffer memory B
2
and an estimate E of the quantity of information contained in the data before compression, or more precisely of the complexity of that data expressed as the sum of the absolute value of the finite differences of the image along its lines. On the basis of these two parameters and a regulation law f, the regulator R
2
determines a compression ratio t from the equation t=f(E, L
B
).
According to this solution, if the quantity of information measured by the estimator E is high during a particular time period (in which case the level L
B
is also high), the compression rate t is increased to prevent saturation of the buffer B
2
.
This solution has many drawbacks:
In practice the quality of the prediction of the compression rate supplied by the estimation E is not constant in the image and can vary considerably. This therefore leads to an equally large variability of the quality of regulation, which must then be compensated by a system (referred to as a skew correction system in this prior art solution) for correcting the prediction error a posteriori. If that system is not used, then the buffer may need to be large, which can increase the complexity of the hardware and the cost, in particular for onboard systems.
It employs a large number of parameters (Par) in the form of a network of prediction straight line segments whose number is proportional to the number of bits on which the input data is coded. Each straight line segment is characterized by the two parameters of an equation. All these parameters are determined empirically, i.e. by carrying out a large number of measurements of the bit rate and complexity as a function of the quantizing step, and finally by applying linear regression to the clouds of points obtained. This method is therefore relatively cumbersome and can be inaccurate, in particular due to the obligation to limit the number of straight line segments obtained, which amounts to limiting the number of quantizing steps that are possible for the regulation function.
Finally, from a practical point of view the method may be difficult to implement in the situation where the bit rate of the input data is high. The computations performed in the regulation loop, in particular the computation of the quantizing step, cannot be performed by an ASIC. A microprocessor is therefore needed. Microprocessors have clock frequencies which are significantly lower than that of an ASIC, which severely limits this type of regulation.
The object of the invention is therefore to alleviate the various drawbacks of the prior art.
SUMMARY OF THE INVENTION
To this end, the present invention firstly provides a processor for transmitting digital data, in particular image data, in a transmission channel, the system including:
a compression system for compressing the data including a decorrelation system, a quantizing system and a coding system, and
a regulation system supplying to the quantizing system at least one quantizing parameter,
the regulation system receiving as input decorrelated data from the decorrelation system and a set point.
The system can further include a storage system at the output of the compression system.
The invention also provides a processing method for transmitting digital data, in particular image data, in a transmission channel, the method including the following ordered steps:
decorrelating the data,
computing a quantizing parameter from a set point and the decorrelated data,
quantizing the decorrelated data in accordance with the quantizing parameter, and
coding the data quantized in the preceding step.
The method can further include a step of storing data at the output of the coding step in a storage system.
In one particular embodiment of the invention the quantizing parameter further depends on measured information from the storage means.
In various embodiments the set point can be a set point bit rate or a set point quality.
Other features of the invention will become clear in the light of the following description of various embodiments of the invention, given with reference to the accompanying drawings.
REFERENCES:
patent: 5134476 (1992-07-01), Aravind et al.
patent: 5246053 (1993-09-01), Jain
patent: 5249053 (1993-09-01), Jain
patent: 5598213 (1997-01-01), Chung
patent: 5745179 (1998-04-01), Senda
patent: 6154493 (2000-11-01), Acharaya et al.
patent: 6310962 (2001-10-01), Chung et al.
patent: 0 239 076 (1987-09-01), None
patent: 0 478 230 (1992-04-01), None
patent: 0 514 663 (1992-11-01), None
patent: 0 540 961 (1993-05-01), None
patent: 0 631 443 (1994-12-01), None
patent: 684 738 (1995-11
Alcatel
Sughrue & Mion, PLLC
Williams Kimberly
Worku Negussie
LandOfFree
System for regulating the bit rate or quality of a digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for regulating the bit rate or quality of a digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for regulating the bit rate or quality of a digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3250026