System for reducing phase difference between clock signals of in

Details System for reducing phase difference between clock signals of in System for reducing phase difference between clock signals of in

1993-12-28

1995-11-07

Lee, Thomas C.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307409, 364270, 3642712, 3649458, 364DIG1, G06F 104

Patent

active

054653479

ABSTRACT:
A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

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