System for reducing delay in instruction execution by executing

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3642306, 3642318, 3642615, 364263, 3642631, 3642712, 3649315, 3649381, 3649382, 364948, 3649483, 364DIG1, 395800, G06F 938

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051270919

ABSTRACT:
A data processing system including a circuit for storing a sequence of instructions, a circuit for determining if the instruction sequence includes a branch instruction, a circuit for storing a sequence of branch target instructions in response to the determination of the existence of a branch instruction in the stored sequence of instructions, a circuit for dispatching instructions in sequence after the branch instruction to a processor to be executed on condition that a branch is to be taken before a determination of whether said branch will be taken and simultaneously for determining if the branch is to be taken, any circuit for directing the processor to execute the instructions in sequence after the branch if the branch is not taken, or, if the branch is to be taken, for dispatching the branch target instruction sequence to the processor for execution.

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IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun., 1986, entitled "Branch-Processing Instruction Cache", pp. 357-359.

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