System for reducing aliasing on a display device

Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C345S419000, C345S530000, C345S543000

Reexamination Certificate

active

07616200

ABSTRACT:
An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique location on the display device. Each sample pattern has at least one sample location. It then is determined if the first image intersects any of the sample locations on each pixel. Pixels determined to have at least one sample location that intersect the first image thus are illuminated.

REFERENCES:
patent: 4434437 (1984-02-01), Strolle et al.
patent: 4615013 (1986-09-01), Yan et al.
patent: 4646232 (1987-02-01), Chang et al.
patent: 4897806 (1990-01-01), Cook et al.
patent: 4908780 (1990-03-01), Priem et al.
patent: 4918626 (1990-04-01), Watkins et al.
patent: 4991122 (1991-02-01), Sanders
patent: 5107415 (1992-04-01), Sato et al.
patent: 5123085 (1992-06-01), Wells et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5287438 (1994-02-01), Kelleher
patent: 5293480 (1994-03-01), Miller et al.
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5363475 (1994-11-01), Baker et al.
patent: 5371840 (1994-12-01), Fischer et al.
patent: 5394524 (1995-02-01), DiNicola et al.
patent: 5398328 (1995-03-01), Weber et al.
patent: 5446479 (1995-08-01), Thompson et al.
patent: 5485559 (1996-01-01), Sakaibara et al.
patent: 5511165 (1996-04-01), Brady et al.
patent: 5519823 (1996-05-01), Barkans
patent: 5544294 (1996-08-01), Cho et al.
patent: 5555359 (1996-09-01), Choi et al.
patent: 5557734 (1996-09-01), Wilson
patent: 5561749 (1996-10-01), Schroeder
patent: 5572713 (1996-11-01), Weber et al.
patent: 5631693 (1997-05-01), Wunderlich et al.
patent: 5664114 (1997-09-01), Krech, Jr. et al.
patent: 5666520 (1997-09-01), Fujita et al.
patent: 5684939 (1997-11-01), Foran et al.
patent: 5701365 (1997-12-01), Harrington et al.
patent: 5706481 (1998-01-01), Hannah et al.
patent: 5721812 (1998-02-01), Mochizuki
patent: 5737455 (1998-04-01), Harrington et al.
patent: 5757375 (1998-05-01), Kawase
patent: 5757385 (1998-05-01), Narayanaswami et al.
patent: 5764237 (1998-06-01), Kaneko
patent: 5821950 (1998-10-01), Rentschler et al.
patent: 5841444 (1998-11-01), Mun et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5883641 (1999-03-01), Krech, Jr. et al.
patent: 5914711 (1999-06-01), Mangerson et al.
patent: 6300956 (2001-10-01), Apodaca et al.
patent: 0 311 798 (1989-04-01), None
patent: 0 397 180 (1990-11-01), None
patent: 0 438 194 (1991-07-01), None
patent: 0 448 286 (1991-09-01), None
patent: 0 463 700 (1992-01-01), None
patent: 0 566 229 (1993-10-01), None
patent: 0 627 682 (1994-12-01), None
patent: 0 631 252 (1994-12-01), None
patent: 0 693 737 (1996-01-01), None
patent: 0 734 008 (1996-09-01), None
patent: 0 735 463 (1996-10-01), None
patent: 0 810 553 (1997-12-01), None
patent: 0 817 009 (1998-01-01), None
patent: 0 825 550 (1998-02-01), None
patent: 0 840 279 (1998-05-01), None
patent: 0 910 047 (1999-04-01), None
patent: WO 86/07646 (1986-12-01), None
patent: WO 92/00570 (1992-01-01), None
patent: WO 93/06553 (1993-04-01), None
patent: WO 97/21192 (1997-06-01), None
patent: WO 97/41536 (1997-11-01), None
“A Fine Grained Data Flow Machine and Its Concurrent Execution Mechanism,” Iwashita et al., C&C Information Technology Research Labs, Apr. 1989, pp. 63-72.
“A Dataflow Image Processing System TIP-4,” Fujita et al., C&C Information Technology Research Labs, NEC Corporation, Sep. 1989, pp. 735-741.
“Processing the New World of Interactive Media,” Rathnam, The Trimedia VLIW CPU Architecture, Mar. 1998, pp. 108-117.
“Effective Cache Mechanism for Texture Mapping,” IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996, pp. 213-217.
“Advanced Raster Graphics Architecture,” pp. 890-893, 1990.
“Data-Format Conversion: Intel/Non-Intel,” vol. 33, No. 1A, Jun. 1990, IBM Technical Disclosure Bulletin, pp. 420-427.
“Address Munging Support in a Memory Controller/PCI Host Bridge for the PowerPC 603 CPU Operating in 32-Bit Data Mode,” IBM Technical Disclosure Bulletin, vol. 38, No. 09, Sep. 1995, pp. 237-240.
“One Frame Ahead: Frame Buffer Management for Animation and Real-Time Graphics,” Auel et al., Tektronix Inc., pp. 43-50, 1988.
“Efficient Alias-Free Rendering Using Bit-Masks and Look-Up Tables,” Abram et al., The University of North Carolina at Chapel Hill, XP-002115680, Jul. 1985, pp. 53-59.
“A New Simple and Efficient Antialiasing with Subpixel Masks,” Schilling et al., Computer Graphics, vol. 25, No. 4, Jul. 1991, pp. 133-141.
“A Multiprocessor System Utilizing Enhanced DSP's for Image Progressing,” Ueda et al., pp. 611-619, 1988.
“The Reyes Image Rendering Architecture,” Cook et al., Computer Graphics, vol. 21, No. 4, Jul. 1987, pp. 95-102.
“The Accumulation Buffer: Hardware Support for High-Quality Rendering,” Haeberli et al., Computer Graphics, vol. 24, No. 4, Aug. 1990, pp. 309-318.
“Advanced Animation and Rendering Techniques,” Watt et al., ACM Press, New York, New York, pp. 127-137, 1988.
The A-Buffer, an Antialiased Hidden Surface Method, Carpenter, Loren, Computer Graphics, vol. 18, No. 3, Jul. 1984, pp. 13-18.
“The A-buffer, an Antialiased Hidden Surface Method,” Loren Carpenter, Computer Graphics, vol. 18, No. 3, pp. 13-18, Jul. 1984.
“Advanced Animation and Rendering Techniques,” Theory and Practice, Alan Watt and Mark Watt, pp. 127-137.
“Efficient Alias-free Rendering using Bit-masks and Look-up Tables,” Greg Abram and Lee Westover,The University of North Carolina at Chapel Hill,, vol. 19, No. 3, 1985.
“A New Simple and Efficient Antialiasing with Subpixel Masks,” Schilling et al., Computer Graphics, vol. 25, No. 4, Jul. 1991, pp. 133-140.
“The Accumulation Buffer: Hardware Support for High-Quality Rendering,” Paul Haeberli et al., Computer Graphics, vol. 24, No. 4, Aug. 1990, pp. 309-318.
“The Reyes Image Rendering Architecture,” Cook et al., Computer Graphics, vol. 21, No. 4, Jul. 1987, pp. 95-102.
“Transparency and Antialiasing Algorithms Implement with the Virtual Pixel Maps Technique,” Mammen et al., IEEE Computer Graphics and Applications, vol. 9, No. 4, Jul. 1, 1989, pp. 43-55.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System for reducing aliasing on a display device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for reducing aliasing on a display device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for reducing aliasing on a display device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4070489

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.