Boots – shoes – and leggings
Patent
1980-10-29
1983-05-17
Thomas, James D.
Boots, shoes, and leggings
365230, G06F 938, G06F 1300
Patent
active
043843425
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
BACKGROUND OF THE INVENTION
The present invention relates to a system for accessing memory modules and, more particularly, to a system for accessing memory modules by using an effective address which is composed of two or more parts, one of which is determined later than the others.
In general, in computer systems, address modification, which changes an address written in a program to an effective address which is actually used for accessing memory modules, has been known and carried out. The address modification is effected by means of a modifier, such as an address mapper or an address modification table. In a small scale computer system, such as a microcomputer system, the number of bits of an effective address is larger than that of an address written in a program. Contrary to this, in a large scale computer system, the number of bits of an effective address is smaller than that of an address written in a program. In any computer system, the lower order bits of an address written in a program serve as a part of an effective address without modification, while the other higher order bits of the address written in the program are changed to the other part of the effective address by a modifier. Therefore, one part of the effective address is determined later than the other part thereof.
In one prior art system for accessing memory modules by using an effective address, one part of which is determined later than the other part thereof, after the entire effective address is determined, the access operation for the memory modules is actually executed. Therefore, the total access time is composed of an address modification time and the actual access time, which means that the speed of access of the memory modules is low.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide a system for accessing memory modules by using an effective address, one part of which is determined later than the other part thereof, with high speed access.
According to the present invention, the average time for accessing memory modules can be reduced by relying on the fact that successive access operations are very frequently executed on the same memory module. Because of this it is advantageous to begin an access operation when the row address portion of an effective address is available, without waiting until the column address and module designation portions of the effective address have been determined. This can be accomplished by providing a first memory address register for storing the column address and module designation portions of the current effective address, a second memory address register for storing the row address portion of the current effective address, and a third memory address register for storing the module designation portion of the prior effective address. The access operation is begun using the module designation portion of the prior effective address, which is stored in the third memory address register, and the row address portion of the current effective address, which is stored in the second memory address register. After the module designation and column address portions of the current effective address are available, a comparator circuit which is connected to the first and third memory address registers determines whether the current and prior effective addresses designate the same memory module. Assuming that the same module is designated, the access operation is completed using the column address portion of the current effective address. In the event that the designated modules are different, however, the modules are accessed again using the module designation, row address, and column address portions of the current effective address. Since the current and previous module designations are very frequently identical, the net result is that the average access time does not reflect the actual address modification time needed for transforming a program address into an effective address.
The present invention will be more clearly understood from the follo
REFERENCES:
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patent: 4156905 (1979-05-01), Fassbender
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patent: 4303993 (1981-12-01), Panepinto, Jr. et al.
patent: 4323965 (1982-04-01), Johnson et al.
patent: 4344131 (1982-08-01), Girard
Imura Takao
Joda Yoshihiro
Koyanagi Shigeru
Panafacom Limited
Thomas James D.
Williams Archie E.
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