Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
2001-11-14
2002-12-03
Eley, Timothy V. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S007000, C451S008000, C451S288000, C451S289000, C451S041000
Reexamination Certificate
active
06488566
ABSTRACT:
TECHNICAL FIELD
This invention relates to systems for polishing semiconductor wafers.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, numerous integrated circuits are typically constructed simultaneously on a single semiconductor wafer. The wafer is then later subjected to a singulation process in which individual integrated circuits are singulated from the wafer. At certain stages of fabrication, it is often necessary to polish a surface of the semiconductor wafer. In general, a semiconductor wafer can be polished to remove high topography, surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. This process is usually performed during the formation of various devices and integrated circuits on the wafer.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This polishing process is often referred to as chemical mechanical planarization (CMP).
In general, the polishing process involves holding and rotating a thin flat wafer of semiconductor material against a polishing surface under controlled pressure and temperature. One such apparatus for polishing thin flat semiconductor wafers is discussed in our U.S. Pat. No. 5,081,796. Other apparatuses are described in U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh.
One problem encountered in polishing processes is the non-uniform removal of the semiconductor surface. Removal rate is directly proportional to downward pressure on the wafer, rotational speeds of the platen and wafer, slurry particle density and size, slurry composition, and the effective area of contact between the polishing pad and the wafer surface. Removal caused by the polishing platen is related to the radial position on the platen. The removal rate is increased as the semiconductor wafer is moved radially outward relative to the polishing platen due to higher platen rotational velocity. Additionally, removal rates tend to be higher at wafer edge than at wafer center because the wafer edge is rotating at a higher speed than the wafer center.
Another problem in conventional polishing processes is the difficulty in removing non-uniform films or layers which have been applied to the semiconductor wafer. During the fabrication of integrated circuits, a particular layer or film may have been deposited or grown in a desired uneven manner resulting in a non-uniform surface which is subsequently subjected to polishing processes. The thicknesses of such layers or films can be very small (on the order of 0.5 to 5.0 microns), thereby allowing little tolerance for non-uniform removal. A similar problem arises when attempting to polish warped surfaces on the semiconductor wafer. Warpage can occur as wafers are subjected to various thermal cycles during the fabrication of integrated circuits. As a result of this warpage, the semiconductor surface has high and low If areas, whereby the high areas will be polished to a greater extent than the low areas.
As a result of these polishing problems, individual regions of the same semiconductor wafer can experience different polishing rates. As an example, one region may be polished at a much higher rate than that of other regions, causing removal of too much material in the high rate region or removal of too little material in the lower rate regions.
A compounding problem associated with polishing semiconductor wafers is the inability to monitor polishing conditions in a effort to detect and correct the above inherent polishing problems as they occur. It is common to conduct numerous pre-polishing measurements of the wafer before commencement of the polishing process, and then conduct numerous similar post-polishing measurements to determine whether the polishing process yielded the desired topography, thickness, and uniformity. However, these pre- and post-polishing measurements are labor intensive and result in a low product throughput.
The present invention provides a polishing system and method which significantly reduces the problems associated with non-uniform removal and monitoring of the polishing process.
REFERENCES:
patent: 5618447 (1997-04-01), Sandhu
patent: 5873769 (1999-02-01), Chiou et al.
patent: 5944580 (1999-08-01), Kim et al.
patent: 6095898 (2000-08-01), Hennhofer et al.
Doan Trung Tri
Sandhu Gurtej S.
Eley Timothy V.
Micro)n Technology, Inc.
Wells St. John P.S.
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