System for reading a double-bit memory cell

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185030, C365S185200

Reexamination Certificate

active

06594181

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to non-volatile semiconductor memory devices, and more particularly, to a system for reading the bits in a double-bit memory cell and associated reference cells.
BACKGROUND OF THE INVENTION
For conventional non-volatile semiconductor devices, such as flash memories, each memory cell stores only one bit of data. For a conventional single bit per cell flash memory architecture, each cell typically includes a metal oxide semiconductor transistor structure having a source, drain, and a channel in a substrate, and a stacked gate structure over a channel. The stacked gate structure typically includes a tunnel oxide formed on the surface of the channel, a floating gate on the tunnel oxide layer, a thin oxide layer over the floating gate, and a control gate overlying the oxide layer. Information is programmed into a flash memory by charging the floating gate for each individual core cell to a predetermined voltage threshold. For a single-bit memory cell, two threshold voltages are predefined such that the data bit is programmed at a threshold that is either a binary “0” or a binary “1”.
Modem devices having non-volatile memory are placing ever increasing demands for larger memory in a small profile package. To satisfy this demand for higher density memory, double-bit per cell (“double-bit cell”) flash memories have been developed. The double-bit cell refers to a cell that allows the storage of two bits of data into a single memory cell.
FIG. 1
is a schematic diagram of the double-bit core cell structure for the present invention. For each double-bit core cell
10
, two bits can be stored and programmed, a first bit identified as the normal bit and a second bit identified as the complementary (“comp”) bit. For a non-volatile memory such as flash memory, the integrity of the data must be maintained over the life of the device to avoid data errors that could adversely impact a user. Over the life of a flash memory cell there can be changes in the cell characteristics which can affect the data. One such change for a cell can occur due to the programming of an adjacent cell over time which disturbs the state of nearby cells. Charge loss over the life of the flash memory can also affect the cell characteristics. These changes in the cell characteristics can result in a shifting of the cell threshold voltages. This shifting can affect the state of the memory cells so as to create data errors. As a result, techniques are needed to assure the integrity of the data bits in a cell over time.
FIG. 2
a
shows two waveforms illustrating an example of the shifting in the distribution of the thresholds for a double-bit cell over time. Since there are two bits in the cell, four threshold distributions are used for the combinations of the two bits. Trace A shows an exemplary state of the voltage threshold distribution for a new memory cell (referred to in
FIG. 1
as “before life”) that has not undergone any programming or read cycling. As memory cells in the array are cycled over the life of the cell array, charge loss, memory disturb, and other changes occur over time that can affect the device characteristics. The changing device characteristics can shift the threshold distribution into a different state. An example of the shifted state (referred to in
FIG. 1
as “after life”) is shown in Trace B. For example, in the traces in
FIG. 2
a
, a (1,0) represents a normal bit equal to 1, and a second “complementary” bit equal to 0. Non-volatile memories such as flash memories might be programmed only once and then read intermittently over a long period of time. There is thus a need to determine the data bit values for the double-bit cell accurately for both threshold distributions shown in Trace A and Trace B. In one technique, two reference thresholds (REF
1
and REF
2
) are provided and compared to the core cell threshold in order to determine the cell data.
FIG. 2
b
illustrates how the technique determines the core cell data from the comparison of the reference thresholds to the normal and complementary bits.
As shown in
FIG. 2
a
and the top and bottom data rows in
FIG. 2
b
, if the core cell threshold lies at either of the two extremes of the distribution, (1,1) or (0,0), only a comparison of the normal bit to the two reference thresholds is required in order to determine the data. For this case, since a comparison with the complementary bit is not needed for determining the cell data, the “comp bit” column in
FIG. 2
b
is marked as an “x” representing a “don't care” state. For example, the core cell data should be “0” when the core cell threshold voltage is higher (identified as “0”) than the two reference thresholds, as shown in the bottom row in
FIG. 2
b
. Conversely, for a core cell threshold voltage lower than the REF
1
and REF
2
thresholds, the data should be “1”.
The shifting of the distribution thresholds over time from Trace A to Trace B, as illustrated by example in
FIG. 2
a
, presents challenges in determining the data for various core cell thresholds. When a core cell threshold lies in the area between the two reference thresholds, the data cannot be determined solely by comparing the normal bit with the two reference thresholds. This is illustrated by
FIG. 2
a
and
FIG. 2
b
, where for a normal bit of 1 for (1,0) in Trace A, and a normal bit of 0 in (0,1) in Trace B, the comparison to the two reference threshold voltages, REF
1
and REF
2
, yields the same result. In order to attempt to provide for proper determination of the data in the two cases, a technique has been developed that provides for two sequential data reads along with reading the two reference thresholds from two reference cells. If both the normal bit and complementary bit can be read along with the reference cells, then the cell data for either the trace A (before life) or Trace B (after life) distribution can be determined, as explained in more detail below.
The advantage of having the complementary bit in addition to the normal bit is illustrated in
FIG. 2
b
. For this technique, when the core cell threshold lies between two reference thresholds, identified as REF
1
and REF
2
, both the normal bit and the complementary bit are compared to REF
1
and REF
2
. For example, for the case above of a normal bit of 0 in (0,1) in Trace B, for this technique the complementary bit threshold lies under the (1,0) distribution, the opposite of the (0,1) distribution. Thus for a core cell threshold between REF
1
and REF
2
, the complementary bit threshold would not be between the two thresholds and thus can be determined. By illustration, the core cell threshold lies in the area under the (0,1) distribution in Trace B between REF
1
and REF
2
. This case is shown in the next to last row of
FIG. 2
b
. For the normal bit, the core cell threshold is higher than REF
1
(shown as “0” in the table) and lower than REF
2
(“1”). For Trace B, the complimentary bit corresponding to this core cell threshold lies under the (1,0) threshold. This complementary bit threshold is lower (“1”) than both REF
1
and REF
2
. This results in a cell data of 0 as shown in
FIG. 2
b.
Similarly, as shown in the third row from the bottom of
FIG. 2
b
, the comparison is the same for the normal bit and REF
1
and REF
2
for the area between REF
1
and REF
2
under the (1,0) distribution in Trace A. Using the complementary bit results in determining the cell data for that case to be a “1”.
For the above technique, by adding a additional comparison of the complementary bit to the reference cells, REF
1
and REF
2
, the cell data can be accurately determined over the life of the cell, even for the case when the core cell threshold lies between the two reference cell thresholds. For the above method, each bit (normal and complementary) is read along with the two reference cells for the reference thresholds REF
1
and REF
2
. The combination of the data read for the reference cells determines the actual cell data. The system and method to provide for the reading of the complementa

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System for reading a double-bit memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for reading a double-bit memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for reading a double-bit memory cell will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3087668

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.