Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-01-04
2001-08-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S205000
Reexamination Certificate
active
06275074
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to electronics, and more particularly to a system for propagating a digital signal through a slew-rate limited node and method of operation.
BACKGROUND OF THE INVENTION
Many switch-mode power supplies use older generation controller integrated circuits (ICs) because they are inexpensive. The output circuits of many of these controller ICs have limited power drive capabilities, and, therefore, do not efficiently drive modern power MOSFETs. Typically, the output circuits of these controller ICs are NPN transistors with open collector terminals. To drive a power MOSFET, the controller IC must generate a rail-to-rail output voltage waveform. This can be accomplished by connecting a resistor between the collector terminal of the NPN transistor and a suitable power supply, and by grounding the emitter terminal. However, the resulting NPN transistor with resistive pull-up suffers several drawbacks when used as a gate driver.
In particular, a MOSFET gate terminal exhibits a large non-linear input capacitance. A large total gate charge is required to slew the gate from one supply rail to the other. Large currents are required to transfer this amount of charge quickly enough to obtain the desired switching times for the MOSFET. The NPN transistor with resistive pull-up cannot generate the high currents required to achieve the desired switching times without the use of a prohibitively small pull-up resistor.
One solution connects an external gate driver circuit between the controller IC and the MOSFET to generate the high currents necessary to slew the large gate capacitance quickly. Generally, a gate driver circuit receives a low current signal to drive a highly capacitive load, such as a power MOSFET. The input signal controls the timing and duration of the high voltage/high current signal output to the load.
Internal and external capacitances and resistances, including those associated with the NPN transistor, cause the output voltage waveform generated by the NPN transistor with resistive pull-up to exhibit large rise and fall times. The resistive pull-up connected to the open-collector NPN transistor in older-generation controller ICs causes the output voltage waveform of the controller IC to rise very slowly. The output voltage waveform therefore exhibits an excessively long rise time. The output voltage waveform may also exhibit a long fall time due to other limitations of older-generation controller ICs.
A gate driver can reduce the rise and fall times of the voltage waveform supplied to the power MOSFET, but propagation delays associated with the rise and fall times of the output voltage waveform of the controller IC will still remain. These propagation delays are undesirable consequences of propagating through a node a digital control signal which exhibits large rise and fall times. Since large rise and fall times are associated with small slew rates, such nodes are said to be slew-rate limited.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a system for reducing the propagation delay of a digital signal through a slew-rate limited node is provided which substantially eliminates or reduces disadvantages and problems associated with prior gate driver systems.
In accordance with one embodiment of the present invention, a system for propagating a digital signal includes a threshold circuit and an output circuit. The threshold circuit includes a comparator circuit that indicates whether an input signal has entered a voltage region, and a memory coupled to the comparator circuit that has a first state if the input signal is rising upon entering the voltage region and a second state if the input signal is falling upon entering the voltage region. The output circuit is coupled to the memory and generates a high output signal when the input signal is within the voltage region and the memory is in the first state. The output circuit generates a low output signal when the input signal is within the voltage region and the memory is in the second state.
Another embodiment of the present invention is a method for propagating a digital signal that includes receiving an input signal and determining whether the input signal is within a voltage region. The method further includes determining a first state if the input signal is rising upon entering the voltage region, and determining a second state if the input signal is falling upon entering the voltage region. The method concludes by generating an output signal. The method generates a high output signal if the input signal is within the voltage region and in the first state. The method generates a low output signal if the input signal is within the voltage region and in the second state.
Technical advantages of the present invention include a system that reduces the propagation delay of a digital signal through a slew-rate limited node. The system allows operation of a switch-mode convertor containing a slew-rate limited node in the gate drive path at higher frequencies than otherwise allowed by prior efforts to minimize delays through the slew-rate limited node. The system further allows the successful transmission of short-duration pulses through a slew-rate limited node, thereby minimizing pulse skipping in a switch-mode convertor which contains a slew-rate limited node in the gate drive path. The system allows the continued application of older generation controller ICs in modern switch-mode power supplies which operate at higher frequencies and over wider ranges of load currents.
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Brady III W. James
Cunningham Terry D.
Moore J. Dennis
Nguyen Long
Telecky , Jr. Frederick J.
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