System for processing single-cycle branch instruction in a pipel

Details System for processing single-cycle branch instruction in a pipel System for processing single-cycle branch instruction in a pipel

1985-08-30

1988-10-11

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 900, G06F 938, G06F 942

Patent

active

047775874

ABSTRACT:
An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

REFERENCES:
patent: 4179731 (1979-12-01), Yamazaki
patent: 4398244 (1983-08-01), Chu et al.
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4471431 (1984-09-01), Vogt
patent: 4498136 (1985-02-01), Sproul, III

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