Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1999-11-23
2004-05-11
Khatri, Anil (Department: 2121)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S241000, C709S241000, C711S170000, C711S203000
Reexamination Certificate
active
06735613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
A field of the invention relates to the allocation of shared resources of a computer system to various applications for which processes are executed as a function of their specific needs. The computer system comprises physical resources, software resources, and an operating system for the resources so that applications can be run on them.
2. Description of Related Art
Among the physical resources, the processors, the physical memory and the input-outputs will essentially be distinguished. The processors execute processes using data and instruction sequences contained in physical memory. The input-outputs allow the processes to exchange data with peripheral devices such as, to give an incomplete list, mass storage devices, printers, telecommunication couplers, screens and keyboards.
Associated in- a known way with the physical memory and the input-outputs is a real address space whose size is adapted to the size of the physical memory and to the number of input-outputs. In order for the execution of the processes not to be limited by the size of the physical memory, the processes have a virtual address space whose size is larger than that of the real address space. The virtual address space is divided into several segments so that each process uses certain segments, either exclusively or in a shared fashion. A segment is constituted by virtual pages, each of which can be mapped to a real page (or frame) of identical size by means of a virtual storage manager. A page fault is generated when a process executes an instruction on a virtual page to which no real page corresponds. The virtual storage manager then takes care of requisitioning a real page, in order to map it to the virtual page, either from the available pages or, if there are no real pages available, from used pages, possibly saving the contents of the real page in mass storage and replacing its mapping. Hence, each page fault slows down the execution of an instruction on a virtual page by the process in question.
For a process, the page fault probability p per instruction decreases when the size of the physical memory, and hence the efficiency e(p) of the system, increases. The current low cost of memory makes it possible to equip the computer system with a physical memory of large size, several gigabytes. If the virtual storage manager uses all of the physical memory for each process, the page fault probability p per instruction is inversely proportional to the size of the physical memory. However, this solution is not entirely satisfactory, and in fact it is noted that the performance of the system does not necessarily increase in a linear fashion with the size of the physical memory. There are many possible causes, such as an increase in the probability of deadlocks in the sharing of resources, widespread fragmentation, which is exacerbated in the case of a non-uniform access memory, and the danger of a requisitioning of the entire memory by one process.
One solution, which consists of allocating the memory in areas of equal-size among processes is unsatisfactory, since dividing the size of the memory by the number of processes increases the page fault probability p and accordingly decreases the efficiency of the system for the processes that require an address space whose size is larger than that of one area.
Another solution consist of assigning each process an area whose size is adapted to its estimated needs and limiting it to stay within that size. This solution also is not very satisfactory since it monopolizes part of the physical memory even if the process is inactive, and it is insensitive to any increase in its needs beyond its estimated needs.
In order to increase the speed of execution of the processes in the system, the latter comprises several processors. Thus, several processes can execute their instructions simultaneously, each executing in a different processor. Moreover, if the execution of a process can be broken down into several instruction streams (or threads) that can be executed in parallel, a process can be executed simultaneously in several processors, each of which is assigned a thread. A scheduler is responsible for allocating the processors to the processes as a function of the availability of the resources. A priori, the more processors the scheduler has at its disposal, the greater the number of threads that can be executed simultaneously. However, it is noted that the performance of the system does not necessarily increase in a linear fashion with the number of processors. There are many possible causes, such as for example the fact that the processes are in contention for the resources of the system.
SUMMARY OF THE INVENTION
To eliminated the drawbacks of the prior art mentioned above, the subject of the invention is a computer system comprising physical resources of the processor type and the physical memory type, for executing processes in a virtual address space by means of a virtual storage manager that maps real pages of physical memory to virtual pages of the virtual address space, and a scheduler for scheduling the execution of threads of the processes in the processors. The computer system comprises at least one named set of physical resources RS, constituted by a given number of identified processors and by a given number of identified real pages, so that the scheduler can have a thread of an identified process executed by one or more of the processors of the set RS, and so that the virtual storage manager can map a real page of the set RS to a virtual page when a page fault caused by the thread appears.
Thus, the execution of a thread of an identified process by one or more processors of the set RS constituted by a given number of identified processors does not disturb the execution of other threads by processors not included in the set RS. The mapping of a real page of the set RS to a virtual page when a page fault caused by this thread appears does not interfere with the mapping of real pages not included in the set RS. The fact that the set RS is named allows it to be recognized by the scheduler and by the manager in connection with an identified process.
REFERENCES:
patent: 5784697 (1998-07-01), Funk et al.
patent: 6105053 (2000-08-01), Kimmel et al.
patent: 0 798 639 (1997-10-01), None
Parsons E.W. et al.: “Coordinated Allocation of Memory and Processors in Multiprocessors”1996 ACM Sigmetrics International Conference on Measurement and Modeling of Computer Systems, Philadelphia, PA, May 23-26, 1996, May 23, 1996, pp. 57-67; XP000679315 Association for Computing Machinery ISBN: 0-89791-793-6 p. 63, left hand column.
Jean-Dominique Sorace
Nasr-Eddine Walehlane
Bull S.A.
Khatri Anil
Kondracki Edward J.
Miles & Stockbridge P.C.
Pham Thomas
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