Patent
1995-03-20
1998-05-26
Harvey, Jack B.
395735, 395868, 395869, 395836, G06F 922
Patent
active
057581703
ABSTRACT:
The present invention discloses a system and method for preventing a computer from initiating new cycles after a user has requested a reboot of the computer. The invention includes a programmable logic device that monitors the reset request (SRESET) signal, and in response places the central processing unit (CPU) of the computer in a hold state. The programmable logic device does this by issuing a hold (HOLD) signal to the CPU and receives back from the CPU a hold acknowledge (HLDA) signal. After the HLDA signal is received, the programmable logic device issues a CPU reset (RESETCPU) signal, which causes the CPU to reset after a certain number of clock cycles have passed. By placing the CPU in a hold state, the programmable logic device prevents the CPU from initiating new cycles just prior to resetting, which could result in corruption of the computer system.
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Felder Daniel
Nguyen Nam
Woodward James Sheldon
Dell USA L.P.
Harvey Jack B.
Phan Raymond N.
Terrile Stephen A.
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