System for pretesting electronic memory locations and automatica

Details System for pretesting electronic memory locations and automatica System for pretesting electronic memory locations and automatica

1976-03-30

1978-01-03

Atkinson, Charles E.

Registers

Systems controlled by data bearing records

Time analysis

365200, 235312, G11C 2900, G06F 1100

Patent

active

040668800

ABSTRACT:
An MOS RAM read/write memory system has thirty-two 1 .times. 512 bit RAM memory chips arranged in a matrix. The system pretests all data bit locations for each address prior to the entry of any data into that address, and automatically skips an address having a faulty data bit location in it. In addition, the system functions, upon reading out of data information from the memory chips, to uniquely identify any faulty MOS RAM memory chip; so that it may be removed and replaced if desired.

REFERENCES:
patent: 3644899 (1972-02-01), Boisvert, Jr.
patent: 3772652 (1973-11-01), Hilberg
patent: 3789205 (1974-01-01), James
patent: 3813032 (1974-05-01), King
patent: 3961252 (1976-06-01), Eichelberger

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