System for placing entries of an outstanding processor request i

Details System for placing entries of an outstanding processor request i System for placing entries of an outstanding processor request i

1995-06-07

1998-04-07

Lee, Thomas C.

395307, 395478, 39549701, G06F 1336, G06F 922

Patent

active

057375470

ABSTRACT:
A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

REFERENCES:
patent: 3654621 (1972-04-01), Bock et al.
patent: 4473880 (1984-09-01), Budde et al.
patent: 4502115 (1985-02-01), Eguchi
patent: 4833655 (1989-05-01), Wolf et al.
patent: 5043981 (1991-08-01), Firoozmand et al.
patent: 5179688 (1993-01-01), Brown et al.
patent: 5208490 (1993-05-01), Yetter
patent: 5249297 (1993-09-01), Brockmann et al.
patent: 5257356 (1993-10-01), Brockmann et al.
patent: 5289403 (1994-02-01), Yetter
patent: 5299158 (1994-03-01), Mason et al.
patent: 5317204 (1994-05-01), Yetter
patent: 5329176 (1994-07-01), Miller, Jr. et al.
patent: 5343096 (1994-08-01), Heikes et al.
patent: 5485586 (1996-01-01), Brash et al.
patent: 5541912 (1996-07-01), Choudhury et al.
patent: 5563920 (1996-10-01), Fimoff et al.
Eric DeLano et al., "A High Speed Superscaler PA-RISC Processor", IEEE, pp. 116-121, 1992.
Doug Hunt, "Advanced Performance Features of the 64-bit PA-8000", IEEE, pp. 123-128, 1995.
Jonathan Lotz et al., "A CMOS RISC CPU Designed for Sustained High Performance on Large Applications", IEEE Journal of Solid-State Circuits, vol. 25, pp. 1190-1198, Oct. 1990.
William Jaffe et al., "A 200MFLOP Precision Architecture Processor", Hewlett-Packard, pp. 1.2.1-1.2.13.

Affiliated with

Also associated with

Rating

System for placing entries of an outstanding processor request i does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for placing entries of an outstanding processor request i, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for placing entries of an outstanding processor request i will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-24252