System for partitioning and testing submodule circuits of an int

Details System for partitioning and testing submodule circuits of an int System for partitioning and testing submodule circuits of an int

1991-06-11

1992-04-21

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 371 225, G01R 3128

Patent

active

051072084

ABSTRACT:
A system for providing testing capability of individual submodules on an integrated circuit module. A test bus having a plurality of conductors is connected to selected internal ports of said submodules through three-way analog switches. Each three-way analog switch provides the capability to observe and control an internal port through combination of the ON/OFF status of two transmission gates. Test patterns for controlling the transmission gates may be provided by onboard D flip-flops which are externally programmed to control or observe ports of an individual submodule.

REFERENCES:
patent: 4286173 (1981-08-01), Oka et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4743841 (1988-05-01), Takeuchi
patent: 4893311 (1990-01-01), Hunter et al.
patent: 4918379 (1990-04-01), Jongepier
McClusky, E. J., "Design . . . "; IEEE Trans on Computers; v. C-30; No. 11; Nov. 1981; pp. 866-874.
Wagner et al; "Design for Testability . . . "; IEEE 1988 Internat. Test Conference, Paper 39.1; 1988; pp. 823-828.
Fasang et al; "Design for Testability . . . "; Proceedings of the IEEE 1988 Custom Integrated Circuits Conference; pp. 16.5.1-16.5.4.

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